diff options
| author | Tony Lindgren <tony@atomide.com> | 2018-12-12 15:46:16 -0800 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2018-12-12 17:50:14 -0800 |
| commit | b8222335938a9c6425b9f14e61c3ca67c8189dfc (patch) | |
| tree | 7171f928412da0b3482e68481292bbbebc92e36c /arch/arm/boot | |
| parent | 5241ccbf2819426e0b55c784105eee7f1c57c9b2 (diff) | |
| download | linux-b8222335938a9c6425b9f14e61c3ca67c8189dfc.tar.bz2 | |
ARM: dts: Fix wrong address for omap5 sata phy
Looks like I missed converting the omap5 sata phy addresses to use offset
from the module base instead of full physical address.
While at it, we can also more it to be a direct child of the interconnect
target module, it is not really a child of the ocp2scp control device.
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/omap5-l4.dtsi | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index 5e00147522b6..2e926dd38b08 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -515,19 +515,19 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0 0x20>; - ranges = <0 0 0x4000>; - sata_phy: phy@4a096000 { - compatible = "ti,phy-pipe3-sata"; - reg = <0x6000 0x80>, /* phy_rx */ - <0x4A096400 0x64>, /* phy_tx */ - <0x4A096800 0x40>; /* pll_ctrl */ - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x374>; - clocks = <&sys_clkin>, - <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; - clock-names = "sysclk", "refclk"; - #phy-cells = <0>; - }; + }; + + sata_phy: phy@6000 { + compatible = "ti,phy-pipe3-sata"; + reg = <0x6000 0x80>, /* phy_rx */ + <0x6400 0x64>, /* phy_tx */ + <0x6800 0x40>; /* pll_ctrl */ + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + syscon-phy-power = <&scm_conf 0x374>; + clocks = <&sys_clkin>, + <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; + clock-names = "sysclk", "refclk"; + #phy-cells = <0>; }; }; |