diff options
| author | David S. Miller <davem@davemloft.net> | 2014-07-30 13:25:49 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-07-30 13:25:49 -0700 |
| commit | f139c74a8df071217dcd63f3ef06ae7be7071c4d (patch) | |
| tree | 5711f695577a18a06dbcd0101956e97b388ffa1a /arch/arm/boot | |
| parent | bd695a5f0ccf7b38982c426d86055ff3591c9b5b (diff) | |
| parent | 26bcd8b72563b4c54892c4c2a409f6656fb8ae8b (diff) | |
| download | linux-f139c74a8df071217dcd63f3ef06ae7be7071c4d.tar.bz2 | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/hi3620.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/omap3-n900.dts | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7791.dtsi | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index ab1116d086be..83a5b8685bd9 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -73,7 +73,7 @@ L2: l2-cache { compatible = "arm,pl310-cache"; - reg = <0xfc10000 0x100000>; + reg = <0x100000 0x100000>; interrupts = <0 15 4>; cache-unified; cache-level = <2>; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 1fe45d1f75ec..b15f1a77d684 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -353,7 +353,7 @@ }; twl_power: power { - compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off"; + compatible = "ti,twl4030-power-n900"; ti,use_poweroff; }; }; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 8d7ffaeff6e0..79f68acfd5d4 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -540,9 +540,9 @@ #clock-cells = <0>; clock-output-names = "sd1"; }; - sd2_clk: sd3_clk@e615007c { + sd2_clk: sd3_clk@e615026c { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615007c 0 4>; + reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-output-names = "sd2"; |