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| author | Thierry Reding <thierry.reding@gmail.com> | 2013-08-09 16:49:28 +0200 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-08-12 14:20:22 -0600 |
| commit | bb034cb5eb7fa6596c40d405e31cef02de21ad30 (patch) | |
| tree | 54ba1bdd2556fd57ba703068bfc0265a36b39608 /arch/arm/boot/dts/tegra30-beaver.dts | |
| parent | 89e7ada41674197387fa67ea0a853f3651b4e375 (diff) | |
| download | linux-bb034cb5eb7fa6596c40d405e31cef02de21ad30.tar.bz2 | |
ARM: tegra: Enable PCIe controller on Beaver
PCIe lane 0 is connected to an onboard Gigabit Ethernet (RTL8168evl) and
lane 4 is routed to the board's miniPCIe slot.
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30-beaver.dts')
| -rw-r--r-- | arch/arm/boot/dts/tegra30-beaver.dts | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 1de4ff6ada88..21660da2ec59 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -10,6 +10,27 @@ reg = <0x80000000 0x7ff00000>; }; + pcie-controller { + status = "okay"; + pex-clk-supply = <&sys_3v3_pexs_reg>; + vdd-supply = <&ldo1_reg>; + avdd-supply = <&ldo2_reg>; + + pci@1,0 { + status = "okay"; + nvidia,num-lanes = <4>; + }; + + pci@2,0 { + status = "okay"; + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + nvidia,num-lanes = <1>; + }; + }; + host1x { hdmi { status = "okay"; |