Merge tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM devicetree updates from Arnd Bergmann:
 "After a somewhat quiet 5.17 release, the size of the DT changes is a
  bit larger again. There are nine new SoC that get added, all of them
  related to existing platforms:

   - Airoha (formerly Mediatek/EcoNet) EN7523 networking SoC and EVB

   - Mediatek mt6582 tablet platform with the Prestigio PMT5008 3G
     tablet

   - Microchip Lan966 networking SoC and it evaluation board

   - Qualcomm Snapdragon 625/632 midrange phone SoCs, with the LG Nexus
     5X and Fairphone FP3 phones

   - Renesas RZ/G2LC and RZ/V2L general-purpose embedded SoCs, along
     with their evaluation boards

   - Samsung Exynos 850 phone SoC and reference board

   - Samsung Exynos7885 with the Samsung Galaxy A8 (2018) phone

   - Tesla FSD (Fully Self-Driving), an automotive SoC loosely derived
     from the Samsung Exynos family.

   - TI K3/AM62 SoC and reference board

  Support for additional functionality in existing dts files is added
  all over the place: Samsung, Renesas, Mstar, wpcm450, OMAP, AT91,
  Allwinner, i.MX, Tegra, Aspeed, Oxnas, Qualcomm, Mediatek, and
  Broadcom.

  Samsung has a rework for its pinctrl schema that is a bit tricky and
  requires driver changes to be included here.

  A few more platforms only have smaller cleanups and DT Schema fixes,
  this includes SoCFPGA, ux500, ixp4xx, STi, Xilinx Zynq, LG, and Juno.

  The new machines are really too many to list, but I'll do it anyway:

  Allwinner:
   - A20-Marsboard development board

  Amlogic:
   - Amediatek X96-AIR (Amlogic S905X3)
   - CYX A95XF3-AIR (Amlogic S905X3)
   - Haochuangy H96-Max (Amlogic S905X3)
   - Amlogic AQ222 (Amlogic S4)
   - OSMC Vero 4K+ (Amlogic S905D)

  Arm Juno:
   - Separate DT depending on SCMI firmware version

  Aspeed:
   - Quanta S6Q BMC (AST2600)
   - ASRock ROMED8HM3 (AST2500)

  Broadcom:
   - Raspberry Pi Zero 2 W

  Marvell MVEBU/Armada:
   - Ctera C200 V1 NAS (kirkwood)
   - Ctera C200 V2 NAS (armada-370)

  Mstar:
   - DongShanPiOne, a low-end embedded board
   - Miyoo Mini handheld game console

  NXP i.MX:
   - Numerous i.MX8M Mini based boards in even more variations, but
    none based on other SoCs this time:
    Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, and
    Gateworks GW7903

  Qualcomm:
   - Google Herobrine R1 Chromebook platform (Snapdragon 7c Gen 3)
   - SHIFT6mq phone (Snapdragon 845)
   - Samsung Galaxy Book2 (Snapdragon 850)
   - Snapdragon 8 Gen 1 Hardware Development Kit

  TI OMAP:
   - SanCloud BeagleBone Enhanced WiFi

  Rockchip:
   - Pine64 PineNote ereader tablet (rk356x)
   - Bananapi-R2-Pro (rk356x)

  STM32:
   - emtrion emSBS-Argon embedded board (stm32mp157c)"

* tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (627 commits)
  arm64: dts: n5x: drop invalid property and fix edac node name
  arm64: dts: fsd: Add the MCT support
  arm64: dts: stingray: Fix spi clock name
  arm64: dts: ns2: Fix spi clock name
  ARM: dts: rockchip: Update regulator name for PX3
  ARM: dts: rockchip: Add #clock-cells value for rk805
  arm64: dts: rockchip: Add #clock-cells value for rk805
  arm64: dts: rockchip: Remove vcc13 and vcc14 for rk808
  arm64: dts: rockchip: Fix SDIO regulator supply properties on rk3399-firefly
  ARM: dts: at91: sama7g5: Add NAND support
  ARM: dts: at91: sama7g5: add eic node
  ARM: dts: at91: sama7g5: Remove unused properties in i2c nodes
  ARM: dts: at91: sam9x60ek: modify vdd_1v5 regulator to vdd_1v15
  arm64: dts: lg: align pl330 node name with dtschema
  arm64: dts: lg: add dma-cells to pl330 node
  arm64: dts: juno: align pl330 node name with dtschema
  arm64: dts: broadcom: Fix sata nodename
  arm64: dts: n5x: add sdr edac support
  arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node
  dt-bindings: usb: dwc2: add disable-over-current
  ...

1 files changed, 70 insertions, 11 deletions

diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi
index 069f95f2b628..d2472cd8f1d0 100644
--- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi
@@ -7,7 +7,7 @@
 
 &pinctrl {
 	sdmmc1_b4_pins_a: sdmmc1-b4-0 {
-		pins1 {
+		pins {
 			pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
 				 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
 				 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
@@ -17,12 +17,6 @@
 			drive-push-pull;
 			bias-disable;
 		};
-		pins2 {
-			pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
-			slew-rate = <2>;
-			drive-push-pull;
-			bias-disable;
-		};
 	};
 
 	sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
@@ -36,16 +30,81 @@
 			bias-disable;
 		};
 		pins2 {
+			pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+			slew-rate = <1>;
+			drive-open-drain;
+			bias-disable;
+		};
+	};
+
+	sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+				 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+				 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+				 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+				 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+				 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+		};
+	};
+
+	sdmmc1_clk_pins_a: sdmmc1-clk-0 {
+		pins {
 			pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
-			slew-rate = <2>;
+			slew-rate = <1>;
 			drive-push-pull;
 			bias-disable;
 		};
-		pins3 {
-			pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+	};
+
+	sdmmc2_b4_pins_a: sdmmc2-b4-0 {
+		pins {
+			pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
+				 <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
+				 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
+				 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
+				 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+			slew-rate = <1>;
+			drive-push-pull;
+			bias-pull-up;
+		};
+	};
+
+	sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
+				 <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
+				 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
+				 <STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */
+			slew-rate = <1>;
+			drive-push-pull;
+			bias-pull-up;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
 			slew-rate = <1>;
 			drive-open-drain;
-			bias-disable;
+			bias-pull-up;
+		};
+	};
+
+	sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
+				 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
+				 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
+				 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
+				 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
+				 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
+		};
+	};
+
+	sdmmc2_clk_pins_a: sdmmc2-clk-0 {
+		pins {
+			pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
+			slew-rate = <1>;
+			drive-push-pull;
+			bias-pull-up;
 		};
 	};