diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-05-16 08:38:17 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-05-16 08:38:17 -0700 |
commit | e8a1d70117116c8d96c266f0b99e931717670eaf (patch) | |
tree | 384082054720dc01ad44f0342faeb80297f7fd8c /arch/arm/boot/dts/rk3288-veyron.dtsi | |
parent | 22c58fd70ca48a29505922b1563826593b08cc00 (diff) | |
parent | 6cbc4d88ad208d6f5b9567bac2fff038e1bbfa77 (diff) | |
download | linux-e8a1d70117116c8d96c266f0b99e931717670eaf.tar.bz2 |
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM Device-tree updates from Olof Johansson:
"Besides new bindings and additional descriptions of hardware blocks
for various SoCs and boards, the main new contents here is:
SoCs:
- Intel Agilex (SoCFPGA)
- NXP i.MX8MM (Quad Cortex-A53 with media/graphics focus)
New boards:
- Allwinner:
+ RerVision H3-DVK (H3)
+ Oceanic 5205 5inMFD (H6)
+ Beelink GS2 (H6)
+ Orange Pi 3 (H6)
- Rockchip:
+ Orange Pi RK3399
+ Nanopi NEO4
+ Veyron-Mighty Chromebook variant
- Amlogic:
+ SEI Robotics SEI510
- ST Micro:
+ stm32mp157a discovery1
+ stm32mp157c discovery2
- NXP:
+ Eckelmann ci4x10 (i.MX6DL)
+ i.MX8MM EVK (i.MX8MM)
+ ZII i.MX7 RPU2 (i.MX7)
+ ZII SPB4 (VF610)
+ Zii Ultra (i.MX8M)
+ TQ TQMa7S (i.MX7Solo)
+ TQ TQMa7D (i.MX7Dual)
+ Kobo Aura (i.MX50)
+ Menlosystems M53 (i.MX53)j
- Nvidia:
+ Jetson Nano (Tegra T210)"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (593 commits)
arm64: dts: bitmain: Add UART pinctrl support for Sophon Edge
arm64: dts: bitmain: Add pinctrl support for BM1880 SoC
arm64: dts: bitmain: Add GPIO Line names for Sophon Edge board
arm64: dts: bitmain: Add GPIO support for BM1880 SoC
ARM: dts: gemini: Indent DIR-685 partition table
dt-bindings: hwmon (pwm-fan) Remove dead "cooling-*-state" properties
ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY
arm64: dts: msm8998: thermal: Restrict thermal zone name length to under 20
arm64: dts: msm8998: thermal: Fix number of supported sensors
arm64: dts: msm8998-mtp: thermal: Remove skin and battery thermal zones
arm64: dts: exynos: Move fixed-clocks out of soc
arm64: dts: exynos: Move pmu and timer nodes out of soc
ARM: dts: s5pv210: Fix camera clock provider on Goni board
ARM: dts: exynos: Properly override node to use MDMA0 on Universal C210
ARM: dts: exynos: Move fixed-clocks out of soc on Exynos3250
ARM: dts: exynos: Remove unneeded address/size cells from fixed-clock on Exynos3250
ARM: dts: exynos: Move pmu and timer nodes out of soc
arm64: dts: rockchip: fix IO domain voltage setting of APIO5 on rockpro64
arm64: dts: db820c: Add sound card support
arm64: dts: apq8096-db820c: Add HDMI display support
...
Diffstat (limited to 'arch/arm/boot/dts/rk3288-veyron.dtsi')
-rw-r--r-- | arch/arm/boot/dts/rk3288-veyron.dtsi | 91 |
1 files changed, 57 insertions, 34 deletions
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 192dbc089ade..1252522392c7 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -60,12 +60,19 @@ pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>; /* - * On the module itself this is one of these (depending - * on the actual card populated): + * Depending on the actual card populated GPIO4 D4 and D5 + * correspond to one of these signals on the module: + * + * D4: * - SDIO_RESET_L_WL_REG_ON * - PDN (power down when low) + * + * D5: + * - BT_I2S_WS_BT_RFDISABLE_L + * - No connect */ - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>, + <&gpio4 RK_PD5 GPIO_ACTIVE_LOW>; }; vcc_5v: vcc-5v { @@ -93,6 +100,23 @@ regulator-boot-on; vin-supply = <&vcc_5v>; }; + + vdd_logic: vdd-logic { + compatible = "pwm-regulator"; + regulator-name = "vdd_logic"; + + pwms = <&pwm1 0 1994 0>; + pwm-supply = <&vcc33_sys>; + + pwm-dutycycle-range = <0x7b 0>; + pwm-dutycycle-unit = <0x94>; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <4000>; + }; }; &cpu0 { @@ -193,8 +217,7 @@ regulator-max-microvolt = <1250000>; regulator-ramp-delay = <6001>; regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; + regulator-off-in-suspend; }; }; @@ -376,10 +399,6 @@ &uart0 { status = "okay"; - /* We need to go faster than 24MHz, so adjust clock parents / rates */ - assigned-clocks = <&cru SCLK_UART0>; - assigned-clock-rates = <48000000>; - /* Pins don't include flow control by default; add that in */ pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; @@ -431,10 +450,14 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = < /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff &global_pwroff >; pinctrl-1 = < /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff &global_pwroff >; @@ -458,13 +481,13 @@ buttons { pwr_key_l: pwr-key-l { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; emmc { emmc_reset: emmc-reset { - rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; }; /* @@ -472,51 +495,51 @@ * We also have external pulls, so disable the internal ones. */ emmc_clk: emmc-clk { - rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>; }; emmc_cmd: emmc-cmd { - rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>; }; emmc_bus8: emmc-bus8 { - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA1 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA2 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA3 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA4 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA5 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA6 2 &pcfg_pull_none_drv_8ma>, + <3 RK_PA7 2 &pcfg_pull_none_drv_8ma>; }; }; pmic { pmic_int_l: pmic-int-l { - rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; reboot { ap_warm_reset_h: ap-warm-reset-h { - rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; recovery-switch { rec_mode_l: rec-mode-l { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; }; }; sdio0 { wifi_enable_h: wifienable-h { - rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; }; /* NOTE: mislabelled on schematic; should be bt_enable_h */ bt_enable_l: bt-enable-l { - rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; /* @@ -524,30 +547,30 @@ * We also have external pulls, so disable the internal ones. */ sdio0_bus4: sdio0-bus4 { - rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>, + <4 RK_PC5 1 &pcfg_pull_none_drv_8ma>, + <4 RK_PC6 1 &pcfg_pull_none_drv_8ma>, + <4 RK_PC7 1 &pcfg_pull_none_drv_8ma>; }; sdio0_cmd: sdio0-cmd { - rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>; }; sdio0_clk: sdio0-clk { - rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>; }; }; tpm { tpm_int_h: tpm-int-h { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; write-protect { fw_wp_ap: fw-wp-ap { - rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; |