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| author | Heiko Stuebner <heiko@sntech.de> | 2017-08-26 14:06:01 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2017-09-22 11:18:08 +0200 |
| commit | 4fcac83b4f2b98f7e9b71d91e44680528b3c2cd4 (patch) | |
| tree | a850668d0701cd21c42b0689f794a51d9f487a33 /arch/arm/boot/dts/rk3066a.dtsi | |
| parent | 451ef43b4385ea17eca4da576d74ced8fdba13b7 (diff) | |
| download | linux-4fcac83b4f2b98f7e9b71d91e44680528b3c2cd4.tar.bz2 | |
ARM: dts: rockchip: add gpu nodes on rk3066/rk3188
The old Cortex-A9 socs use Mali400 GPUs with 4 pixel processors.
This adds the core gpu nodes with the per-soc interrupts but sharing
the core node.
Rockchip SoCs use only one clock to supply the GPUs
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3066a.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/rk3066a.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index f50481fd8e5c..b76119dd5733 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -610,6 +610,30 @@ }; }; +&gpu { + compatible = "rockchip,rk3066-mali", "arm,mali-400"; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "pp0mmu", + "pp1", + "pp1mmu", + "pp2", + "pp2mmu", + "pp3", + "pp3mmu"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_xfer>; |