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author | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-01-14 12:13:00 +0100 |
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committer | Simon Horman <horms+renesas@verge.net.au> | 2015-01-15 08:54:24 +0900 |
commit | 35dd549cb300e346e2f2ec1f12dd9cd245b3276b (patch) | |
tree | d53959cf5255fda57356e01a4bac82c73127b076 /arch/arm/boot/dts/r8a73a4.dtsi | |
parent | 753b9c9cfdfeae57f956c55e1ccdfcf2d90e6196 (diff) | |
download | linux-35dd549cb300e346e2f2ec1f12dd9cd245b3276b.tar.bz2 |
ARM: shmobile: r8a73a4 dtsi: Add memory-controller nodes
Add device nodes for the two DDR Bus State Controllers (DBSC).
The DBSCs are located in the A3BC PM domain, which must not be powered
down, else the system will crash.
A reference to the A3BC PM domain will be added later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a73a4.dtsi')
-rw-r--r-- | arch/arm/boot/dts/r8a73a4.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 5ac57babc3b9..38136d9f6d95 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -38,6 +38,16 @@ <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + dbsc1: memory-controller@e6790000 { + compatible = "renesas,dbsc-r8a73a4"; + reg = <0 0xe6790000 0 0x10000>; + }; + + dbsc2: memory-controller@e67a0000 { + compatible = "renesas,dbsc-r8a73a4"; + reg = <0 0xe67a0000 0 0x10000>; + }; + dmac: dma-multiplexer { compatible = "renesas,shdma-mux"; #dma-cells = <1>; |