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author | Sricharan R <sricharan@codeaurora.org> | 2018-05-25 11:41:18 +0530 |
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committer | Andy Gross <andy.gross@linaro.org> | 2018-05-25 15:40:21 -0500 |
commit | 5ade893ec03c6612a38d53eaf4324f21e18eeef5 (patch) | |
tree | e8e4d7e913d93fefeac693a3dd974323eb399fb1 /arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | |
parent | f97b2aaaf0734a3a6dd6effff6ee0aaa0a69cab5 (diff) | |
download | linux-5ade893ec03c6612a38d53eaf4324f21e18eeef5.tar.bz2 |
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts')
-rw-r--r-- | arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts new file mode 100644 index 000000000000..8c7ef6537ae6 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, The Linux Foundation. All rights reserved. + +#include "qcom-ipq4019-ap.dk07.1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1"; + compatible = "qcom,ipq4019-ap-dk07.1-c1"; + + soc { + pci@40000000 { + status = "ok"; + perst-gpio = <&tlmm 38 0x1>; + }; + + spi@78b6000 { + status = "ok"; + }; + + pinctrl@1000000 { + serial_1_pins: serial1-pinmux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_uart1"; + bias-disable; + }; + + spi_0_pins: spi-0-pinmux { + pinmux { + function = "blsp_spi0"; + pins = "gpio13", "gpio14", "gpio15"; + bias-disable; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio12"; + bias-disable; + output-high; + }; + }; + }; + + serial@78b0000 { + pinctrl-0 = <&serial_1_pins>; + pinctrl-names = "default"; + status = "ok"; + }; + + spi@78b5000 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "ok"; + cs-gpios = <&tlmm 12 0>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "n25q128a11"; + spi-max-frequency = <24000000>; + }; + }; + }; +}; |