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authorStefan Agner <stefan@agner.ch>2017-12-19 19:10:33 +0100
committerShawn Guo <shawnguo@kernel.org>2017-12-26 16:15:44 +0800
commitc2e70bbb616d8605b86b3344ccc03d122b5d8494 (patch)
tree0f4d67de7e19aa5e265ba9fb5997359b6ef9e64f /arch/arm/boot/dts/imx7-colibri.dtsi
parentffb2e259c462b38f4cccf742d6d9856429725ed0 (diff)
downloadlinux-c2e70bbb616d8605b86b3344ccc03d122b5d8494.tar.bz2
ARM: dts: imx7-colibri: use NAND_CE1 as GPIO
All Colibri iMX7 SKUs use either single-die NAND or eMMC, hence NAND_CE1 is not used on the module and can be used as a GPIO by carrier boards. Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx7-colibri.dtsi')
-rw-r--r--arch/arm/boot/dts/imx7-colibri.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index e4e32aa786f4..f61041af026a 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -329,6 +329,7 @@
MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */
MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */
MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */
+ MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */
MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */
MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */
@@ -439,7 +440,6 @@
MX7D_PAD_SD3_CLK__NAND_CLE 0x71
MX7D_PAD_SD3_CMD__NAND_ALE 0x71
MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
- MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71
MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71