diff options
author | Tim Harvey <tharvey@gateworks.com> | 2014-09-08 23:07:30 -0700 |
---|---|---|
committer | Shawn Guo <shawn.guo@freescale.com> | 2014-09-16 10:27:20 +0800 |
commit | b5f37b76053afe8863ce9a753903932eb542eca9 (patch) | |
tree | 1bbc5345afd12d6e3771312c7b826f10e8ffeb2e /arch/arm/boot/dts/imx6q-gw5400-a.dts | |
parent | 73e005c111bc3f77ca3793d465539a11e7604c71 (diff) | |
download | linux-b5f37b76053afe8863ce9a753903932eb542eca9.tar.bz2 |
ARM: dts: imx: ventana: cleanup pinctrl groups
Follow the conventions for pinctrl:
- grouping pinctrl in logical alphabatized groups
- remove any pinctrl not being used by a driver or needed by user
- move iomuxc to bottom of file for readability
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6q-gw5400-a.dts')
-rw-r--r-- | arch/arm/boot/dts/imx6q-gw5400-a.dts | 157 |
1 files changed, 83 insertions, 74 deletions
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index eb28f631279e..822ffb231c57 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -38,6 +38,8 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; led0: user1 { label = "user1"; @@ -65,6 +67,8 @@ pps { compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -337,27 +341,64 @@ }; }; -&iomuxc { +&ldb { + status = "okay"; +}; + +&pcie { + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; + + eth1: sky2@8 { /* MAC/PHY on bus 8 */ + compatible = "marvell,sky2"; + }; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&iomuxc { imx6q-gw5400-a { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0001b0b0 /* SPINOR_CS0# */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0001b0b0 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE RST */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0001b0b0 /* GPS_PPS */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b0b0 /* TOUCH_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0001b0b0 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */ - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x4001b0b0 /* USBHUB_RST# */ - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x4001b0b0 /* MIPI_DIO */ - >; - }; pinctrl_audmux: audmuxgrp { fsl,pins = < @@ -365,6 +406,7 @@ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ >; }; @@ -373,6 +415,7 @@ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */ >; }; @@ -397,6 +440,14 @@ >; }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */ + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 @@ -418,6 +469,19 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 @@ -442,6 +506,7 @@ pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ >; }; @@ -457,59 +522,3 @@ }; }; }; - -&ldb { - status = "okay"; -}; - -&pcie { - reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; - - eth1: sky2@8 { /* MAC/PHY on bus 8 */ - compatible = "marvell,sky2"; - }; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; |