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| author | Vineet Gupta <vgupta@synopsys.com> | 2016-10-31 13:06:19 -0700 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2016-11-30 11:54:25 -0800 |
| commit | b26c2e3823bae6ba43a2b263d9bb75a3efd39b6a (patch) | |
| tree | 9db1449b325dcb708de12e3be54c16890774e9ff /arch/arc | |
| parent | 2d7f5c48c03ee53ad649cbf803dc33730f955234 (diff) | |
| download | linux-b26c2e3823bae6ba43a2b263d9bb75a3efd39b6a.tar.bz2 | |
ARC: breakout timer include code into separate header ...
... which allows for use in drivers/clocksource later
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/include/asm/arcregs.h | 9 | ||||
| -rw-r--r-- | arch/arc/kernel/time.c | 18 |
2 files changed, 4 insertions, 23 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 7a2c36e83186..da41a54ea2d7 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -20,7 +20,6 @@ #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */ #define ARC_REG_SLC_BCR 0xce #define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */ -#define ARC_REG_TIMERS_BCR 0x75 #define ARC_REG_AP_BCR 0x76 #define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */ #define ARC_REG_XY_MEM_BCR 0x79 @@ -208,13 +207,7 @@ struct bcr_fp_arcv2 { #endif }; -struct bcr_timer { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8; -#else - unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15; -#endif -}; +#include <soc/arc/timers.h> struct bcr_bpu_arcompact { #ifdef CONFIG_CPU_BIG_ENDIAN diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c index ec1b896f27b2..94b9cd169374 100644 --- a/arch/arc/kernel/time.c +++ b/arch/arc/kernel/time.c @@ -38,22 +38,10 @@ #include <linux/of.h> #include <linux/of_irq.h> #include <asm/irq.h> -#include <asm/arcregs.h> +#include <soc/arc/timers.h> #include <soc/arc/mcip.h> -/* Timer related Aux registers */ -#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ -#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ -#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ -#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */ -#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ -#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ - -#define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */ -#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ - -#define ARC_TIMER_MAX 0xFFFFFFFF static unsigned long arc_timer_freq; @@ -218,7 +206,7 @@ static int __init arc_cs_setup_timer1(struct device_node *node) if (ret) return ret; - write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX); + write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX); write_aux_reg(ARC_REG_TIMER1_CNT, 0); write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); @@ -296,7 +284,7 @@ static int arc_timer_starting_cpu(unsigned int cpu) evt->cpumask = cpumask_of(smp_processor_id()); - clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMER_MAX); + clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX); enable_percpu_irq(arc_timer_irq, 0); return 0; } |