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authorTal Zilcer <talz@ezchip.com>2015-03-09 16:58:39 +0200
committerVineet Gupta <vgupta@synopsys.com>2016-05-09 09:32:33 +0530
commit46c3e6b8768643d9bc7325324d17e37781b7bbf8 (patch)
tree5445aadde2958c2ec23bc7947969e980208a481f /arch/arc
parent86c25466f7414d6396f1aaa13e4b34f36ec272d5 (diff)
downloadlinux-46c3e6b8768643d9bc7325324d17e37781b7bbf8.tar.bz2
ARC: [plat-eznps] Use dedicated cpu_relax()
Since the CTOP is SMT hardware multi-threaded, we need to hint the HW that now will be a very good time to do a hardware thread context switching. This is done by issuing the schd.rw instruction (binary coded here so as to not require specific revision of GCC to build the kernel). sched.rw means that Thread becomes eligible for execution by the threads scheduler after all pending read/write transactions were completed. Implementing cpu_relax_lowlatency() with barrier() Since with current semantics of cpu_relax() it may take a while till yielded CPU will get back. Signed-off-by: Noam Camus <noamc@ezchip.com> Cc: Peter Zijlstra <peterz@infradead.org> Acked-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc')
-rw-r--r--arch/arc/include/asm/processor.h14
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index 194a09fce198..f9048994b22f 100644
--- a/arch/arc/include/asm/processor.h
+++ b/arch/arc/include/asm/processor.h
@@ -57,9 +57,19 @@ struct task_struct;
* A lot of busy-wait loops in SMP are based off of non-volatile data otherwise
* get optimised away by gcc
*/
-#define cpu_relax() __asm__ __volatile__ ("" : : : "memory")
+#ifndef CONFIG_EZNPS_MTM_EXT
-#define cpu_relax_lowlatency() cpu_relax()
+#define cpu_relax() barrier()
+#define cpu_relax_lowlatency() cpu_relax()
+
+#else
+
+#define cpu_relax() \
+ __asm__ __volatile__ (".word %0" : : "i"(CTOP_INST_SCHD_RW) : "memory")
+
+#define cpu_relax_lowlatency() barrier()
+
+#endif
#define copy_segments(tsk, mm) do { } while (0)
#define release_segments(mm) do { } while (0)