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| author | Vineet Gupta <vgupta@kernel.org> | 2020-10-01 16:42:15 -0700 |
|---|---|---|
| committer | Vineet Gupta <vgupta@kernel.org> | 2021-08-25 15:53:19 -0700 |
| commit | f35534a2bcc7fd614a11aa7e3d91a0b1d6c962fb (patch) | |
| tree | 5a65961d1b3e4e0097221f106a10e6941304dca5 /arch/arc | |
| parent | fe6cb7b043b69cd9498616592bb9e28648fb4f7a (diff) | |
| download | linux-f35534a2bcc7fd614a11aa7e3d91a0b1d6c962fb.tar.bz2 | |
ARC: mm: hack to allow 2 level build with 4 level code
PMD_SHIFT is mapped to PUD_SHIFT or PGD_SHIFT by asm-generic/pgtable-*
but only for !__ASSEMBLY__
tlbex.S asm code has PTRS_PER_PTE which uses PMD_SHIFT hence barfs
for CONFIG_PGTABLE_LEVEL={2,3} and works for 4.
So add a workaround local to tlbex.S - the proper fix is to change
asm-generic/pgtable-* headers to expose the defines for __ASSEMBLY__ too
Signed-off-by: Vineet Gupta <vgupta@kernel.org>
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/mm/tlbex.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S index 0b4bb62fa0ab..c4a5f16444ce 100644 --- a/arch/arc/mm/tlbex.S +++ b/arch/arc/mm/tlbex.S @@ -145,6 +145,14 @@ ex_saved_reg1: ;TLB Miss handling Code ;============================================================================ +#ifndef PMD_SHIFT +#define PMD_SHIFT PUD_SHIFT +#endif + +#ifndef PUD_SHIFT +#define PUD_SHIFT PGDIR_SHIFT +#endif + ;----------------------------------------------------------------------------- ; This macro does the page-table lookup for the faulting address. ; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address |