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| author | Vineet Gupta <vgupta@synopsys.com> | 2013-09-05 13:03:35 +0530 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2013-11-06 10:41:29 +0530 |
| commit | f3e4de327403cee6f76c0dca1b45d6fb0b08daf4 (patch) | |
| tree | 15ff0625f7848aac0b8d436f497a17a5fd5a4144 /arch/arc | |
| parent | 064a6269245655b15054ad9783bca9bfd8dc1f9e (diff) | |
| download | linux-f3e4de327403cee6f76c0dca1b45d6fb0b08daf4.tar.bz2 | |
ARC: cacheflush refactor #1: push aux reg ascertaining into leaf routine
ARC dcache supports 3 ops - Inv, Flush, Flush-n-Inv.
The programming model however provides 2 commands FLUSH, INV.
INV will either discard or flush-n-discard (based on DT_CTRL bit)
The leaf helper __dc_line_loop() used to take the AUX register
(corresponding to the 2 commands). Now we push that to within the
helper, paving way for code consolidations to follow.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/mm/cache_arc700.c | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c index 5a1259cd948c..2787e5a2c306 100644 --- a/arch/arc/mm/cache_arc700.c +++ b/arch/arc/mm/cache_arc700.c @@ -296,8 +296,10 @@ static inline void __dc_entire_op(const int cacheop) * (aliasing VIPT dcache flushing needs both vaddr and paddr) */ static inline void __dc_line_loop(unsigned long paddr, unsigned long vaddr, - unsigned long sz, const int aux_reg) + unsigned long sz, const int cacheop) { + /* which MMU cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ + const int aux = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; int num_lines; /* Ensure we properly floor/ceil the non-line aligned/sized requests @@ -326,11 +328,11 @@ static inline void __dc_line_loop(unsigned long paddr, unsigned long vaddr, */ write_aux_reg(ARC_REG_DC_PTAG, paddr); - write_aux_reg(aux_reg, vaddr); + write_aux_reg(aux, vaddr); vaddr += ARC_DCACHE_LINE_LEN; #else /* paddr contains stuffed vaddrs bits */ - write_aux_reg(aux_reg, paddr); + write_aux_reg(aux, paddr); #endif paddr += ARC_DCACHE_LINE_LEN; } @@ -346,7 +348,6 @@ static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr, unsigned long sz, const int cacheop) { unsigned long flags, tmp = tmp; - int aux; local_irq_save(flags); @@ -361,12 +362,7 @@ static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr, write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH); } - if (cacheop & OP_INV) /* Inv / flush-n-inv use same cmd reg */ - aux = ARC_REG_DC_IVDL; - else - aux = ARC_REG_DC_FLDL; - - __dc_line_loop(paddr, vaddr, sz, aux); + __dc_line_loop(paddr, vaddr, sz, cacheop); if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */ wait_for_flush(); |