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| author | Vineet Gupta <vgupta@synopsys.com> | 2014-11-13 19:27:24 +0530 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2019-10-28 12:12:31 -0700 |
| commit | cfd9d70a855edf6adb37d0ed88be9e35274dbe49 (patch) | |
| tree | 3be75666a3101764e58a227672dbf5e25f945da4 /arch/arc/mm/tlb.c | |
| parent | 7b491c0b62594a21cab357e0118603830a500de3 (diff) | |
| download | linux-cfd9d70a855edf6adb37d0ed88be9e35274dbe49.tar.bz2 | |
ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg
ARC700 exception (and intr handling) didn't have auto stack switching
thus had to rely on stashing a reg temporarily (to free it up) at a
known place in memory, allowing to code up the low level stack switching.
This however was not re-entrant in SMP which thus had to repurpose the
per-cpu MMU SCRATCH DATA register otherwise used to "cache" the task pdg
pointer (vs. reading it from mm struct)
The newer HS cores do have auto-stack switching and thus even SMP builds
can use the MMU SCRATCH reg as originally intended.
This patch fixes the restriction to ARC700 SMP builds only
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/mm/tlb.c')
| -rw-r--r-- | arch/arc/mm/tlb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c index 10025e199353..417f05ac4397 100644 --- a/arch/arc/mm/tlb.c +++ b/arch/arc/mm/tlb.c @@ -868,7 +868,7 @@ void arc_mmu_init(void) write_aux_reg(ARC_REG_PID, MMU_ENABLE); /* In smp we use this reg for interrupt 1 scratch */ -#ifndef CONFIG_SMP +#ifdef ARC_USE_SCRATCH_REG /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */ write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir); #endif |