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authorLinus Torvalds <torvalds@linux-foundation.org>2017-09-08 16:02:18 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2017-09-08 16:02:18 -0700
commitee89252b9edf08a8be3a4f5db53c56d39c872822 (patch)
tree1cc9bf64e5d4edc57125a650b3f7b9522b892a7e /arch/arc/kernel
parent0d519f2d1ed1f11e49abc88cfcf6cf13b83ba14c (diff)
parent1ee55a8f7f6b7ca4c0c59e0b4b4e3584a085c2d3 (diff)
downloadlinux-ee89252b9edf08a8be3a4f5db53c56d39c872822.tar.bz2
Merge tag 'arc-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC updates from Vineet Gupta: - Support for HSDK board hosting a Quad core HS38x4 based SoC running @1GHz (and some prerrquisite changes such as ability to scoot the kernel code/data from start of memory map etc) - Quite a few updates for EZChip (Mellanox) platform - Fixes to fault/exception printing * tag 'arc-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (26 commits) ARC: Re-enable MMU upon Machine Check exception ARC: Show fault information passed to show_kernel_fault_diag() ARC: [plat-hsdk] initial port for HSDK board ARC: mm: Decouple RAM base address from kernel link address ARCv2: IOC: Tighten up the contraints (specifically base / size alignment) ARC: [plat-axs103] refactor the DT fudging code ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk ARC: [plat-axs103] use clk driver #1: Get rid of platform specific cpu clk setting ARCv2: SLC: provide a line based flush routine for debugging ARC: Hardcode ARCH_DMA_MINALIGN to max line length we may have ARC: [plat-eznps] handle extra aux regs #2: kernel/entry exit ARC: [plat-eznps] handle extra aux regs #1: save/restore on context switch ARC: [plat-eznps] avoid toggling of DPC register ARC: [plat-eznps] Update the init sequence of aux regs per cpu. ARC: [plat-eznps] new command line argument for HW scheduler at MTM ARC: set boot print log level to PR_INFO ARC: [plat-eznps] Handle user memory error same in simulation and silicon ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle task ARC: create cpu specific version of arch_cpu_idle() ARC: [plat-eznps] spinlock aware for MTM ...
Diffstat (limited to 'arch/arc/kernel')
-rw-r--r--arch/arc/kernel/devtree.c5
-rw-r--r--arch/arc/kernel/entry-compact.S22
-rw-r--r--arch/arc/kernel/entry.S6
-rw-r--r--arch/arc/kernel/process.c33
-rw-r--r--arch/arc/kernel/setup.c6
-rw-r--r--arch/arc/kernel/traps.c4
-rw-r--r--arch/arc/kernel/troubleshoot.c5
7 files changed, 60 insertions, 21 deletions
diff --git a/arch/arc/kernel/devtree.c b/arch/arc/kernel/devtree.c
index 3b67f538f142..521ef3521a1c 100644
--- a/arch/arc/kernel/devtree.c
+++ b/arch/arc/kernel/devtree.c
@@ -29,8 +29,9 @@ static void __init arc_set_early_base_baud(unsigned long dt_root)
{
if (of_flat_dt_is_compatible(dt_root, "abilis,arc-tb10x"))
arc_base_baud = 166666666; /* Fixed 166.6MHz clk (TB10x) */
- else if (of_flat_dt_is_compatible(dt_root, "snps,arc-sdp"))
- arc_base_baud = 33333333; /* Fixed 33MHz clk (AXS10x) */
+ else if (of_flat_dt_is_compatible(dt_root, "snps,arc-sdp") ||
+ of_flat_dt_is_compatible(dt_root, "snps,hsdk"))
+ arc_base_baud = 33333333; /* Fixed 33MHz clk (AXS10x & HSDK) */
else if (of_flat_dt_is_compatible(dt_root, "ezchip,arc-nps"))
arc_base_baud = 800000000; /* Fixed 800MHz clk (NPS) */
else
diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S
index 9211707634dc..f285dbb28066 100644
--- a/arch/arc/kernel/entry-compact.S
+++ b/arch/arc/kernel/entry-compact.S
@@ -25,12 +25,12 @@
*
* vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
* -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
- * -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
+ * -Wrappers for sys_{,rt_}sigsuspend() no longer needed as they don't
* need ptregs anymore
*
* Vineetg: Oct 2009
* -In a rare scenario, Process gets a Priv-V exception and gets scheduled
- * out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
+ * out. Since we don't do FAKE RTIE for Priv-V, CPU exception state remains
* active (AE bit enabled). This causes a double fault for a subseq valid
* exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
* Instr Error could also cause similar scenario, so same there as well.
@@ -59,7 +59,7 @@
*/
#include <linux/errno.h>
-#include <linux/linkage.h> /* {EXTRY,EXIT} */
+#include <linux/linkage.h> /* {ENTRY,EXIT} */
#include <asm/entry.h>
#include <asm/irqflags.h>
@@ -80,8 +80,8 @@
.align 4
/* Each entry in the vector table must occupy 2 words. Since it is a jump
- * across sections (.vector to .text) we are gauranteed that 'j somewhere'
- * will use the 'j limm' form of the intrsuction as long as somewhere is in
+ * across sections (.vector to .text) we are guaranteed that 'j somewhere'
+ * will use the 'j limm' form of the instruction as long as somewhere is in
* a section other than .vector.
*/
@@ -105,13 +105,13 @@ VECTOR handle_interrupt_level1 ; Other devices
; ******************** Exceptions **********************
VECTOR EV_MachineCheck ; 0x100, Fatal Machine check (0x20)
-VECTOR EV_TLBMissI ; 0x108, Intruction TLB miss (0x21)
+VECTOR EV_TLBMissI ; 0x108, Instruction TLB miss (0x21)
VECTOR EV_TLBMissD ; 0x110, Data TLB miss (0x22)
VECTOR EV_TLBProtV ; 0x118, Protection Violation (0x23)
; or Misaligned Access
VECTOR EV_PrivilegeV ; 0x120, Privilege Violation (0x24)
VECTOR EV_Trap ; 0x128, Trap exception (0x25)
-VECTOR EV_Extension ; 0x130, Extn Intruction Excp (0x26)
+VECTOR EV_Extension ; 0x130, Extn Instruction Excp (0x26)
.rept 24
VECTOR reserved ; Reserved Exceptions
@@ -199,7 +199,7 @@ END(handle_interrupt_level2)
; ---------------------------------------------
; User Mode Memory Bus Error Interrupt Handler
-; (Kernel mode memory errors handled via seperate exception vectors)
+; (Kernel mode memory errors handled via separate exception vectors)
; ---------------------------------------------
ENTRY(mem_service)
@@ -273,7 +273,7 @@ ENTRY(EV_TLBProtV)
;------ (5) Type of Protection Violation? ----------
;
; ProtV Hardware Exception is triggered for Access Faults of 2 types
- ; -Access Violaton : 00_23_(00|01|02|03)_00
+ ; -Access Violation : 00_23_(00|01|02|03)_00
; x r w r+w
; -Unaligned Access : 00_23_04_00
;
@@ -327,7 +327,7 @@ END(call_do_page_fault)
.Lrestore_regs:
- # Interrpts are actually disabled from this point on, but will get
+ # Interrupts are actually disabled from this point on, but will get
# reenabled after we return from interrupt/exception.
# But irq tracer needs to be told now...
TRACE_ASM_IRQ_ENABLE
@@ -335,7 +335,7 @@ END(call_do_page_fault)
lr r10, [status32]
; Restore REG File. In case multiple Events outstanding,
- ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
+ ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
; Note that we use realtime STATUS32 (not pt_regs->status32) to
; decide that.
diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
index 1eea99beecc3..85d9ea4a0acc 100644
--- a/arch/arc/kernel/entry.S
+++ b/arch/arc/kernel/entry.S
@@ -92,6 +92,12 @@ ENTRY(EV_MachineCheck)
lr r0, [efa]
mov r1, sp
+ ; hardware auto-disables MMU, re-enable it to allow kernel vaddr
+ ; access for say stack unwinding of modules for crash dumps
+ lr r3, [ARC_REG_PID]
+ or r3, r3, MMU_ENABLE
+ sr r3, [ARC_REG_PID]
+
lsr r3, r2, 8
bmsk r3, r3, 7
brne r3, ECR_C_MCHK_DUP_TLB, 1f
diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
index 2a018de6d6cd..5ac3b547453f 100644
--- a/arch/arc/kernel/process.c
+++ b/arch/arc/kernel/process.c
@@ -79,15 +79,40 @@ done:
return uval;
}
+#ifdef CONFIG_ISA_ARCV2
+
void arch_cpu_idle(void)
{
- /* sleep, but enable all interrupts before committing */
+ /* Re-enable interrupts <= default irq priority before commiting SLEEP */
+ const unsigned int arg = 0x10 | ARCV2_IRQ_DEF_PRIO;
+
__asm__ __volatile__(
"sleep %0 \n"
:
- :"I"(ISA_SLEEP_ARG)); /* can't be "r" has to be embedded const */
+ :"I"(arg)); /* can't be "r" has to be embedded const */
+}
+
+#elif defined(CONFIG_EZNPS_MTM_EXT) /* ARC700 variant in NPS */
+
+void arch_cpu_idle(void)
+{
+ /* only the calling HW thread needs to sleep */
+ __asm__ __volatile__(
+ ".word %0 \n"
+ :
+ :"i"(CTOP_INST_HWSCHD_WFT_IE12));
+}
+
+#else /* ARC700 */
+
+void arch_cpu_idle(void)
+{
+ /* sleep, but enable both set E1/E2 (levels of interrutps) before committing */
+ __asm__ __volatile__("sleep 0x3 \n");
}
+#endif
+
asmlinkage void ret_from_fork(void);
/*
@@ -209,6 +234,10 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long usp)
*/
regs->status32 = STATUS_U_MASK | STATUS_L_MASK | ISA_INIT_STATUS_BITS;
+#ifdef CONFIG_EZNPS_MTM_EXT
+ regs->eflags = 0;
+#endif
+
/* bogus seed values for debugging */
regs->lp_start = 0x10;
regs->lp_end = 0x80;
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 666613fde91d..c4ffb441716c 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -385,13 +385,13 @@ void setup_processor(void)
read_arc_build_cfg_regs();
arc_init_IRQ();
- printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
+ pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
arc_mmu_init();
arc_cache_init();
- printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
- printk(arc_platform_smp_cpuinfo());
+ pr_info("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
+ pr_info("%s", arc_platform_smp_cpuinfo());
arc_chk_core_config();
}
diff --git a/arch/arc/kernel/traps.c b/arch/arc/kernel/traps.c
index ff83e78d0cfb..bcd7c9fc5d0f 100644
--- a/arch/arc/kernel/traps.c
+++ b/arch/arc/kernel/traps.c
@@ -80,7 +80,7 @@ int name(unsigned long address, struct pt_regs *regs) \
DO_ERROR_INFO(SIGILL, "Priv Op/Disabled Extn", do_privilege_fault, ILL_PRVOPC)
DO_ERROR_INFO(SIGILL, "Invalid Extn Insn", do_extension_fault, ILL_ILLOPC)
DO_ERROR_INFO(SIGILL, "Illegal Insn (or Seq)", insterror_is_error, ILL_ILLOPC)
-DO_ERROR_INFO(SIGBUS, "Invalid Mem Access", do_memory_error, BUS_ADRERR)
+DO_ERROR_INFO(SIGBUS, "Invalid Mem Access", __weak do_memory_error, BUS_ADRERR)
DO_ERROR_INFO(SIGTRAP, "Breakpoint Set", trap_is_brkpt, TRAP_BRKPT)
DO_ERROR_INFO(SIGBUS, "Misaligned Access", do_misaligned_error, BUS_ADRALN)
@@ -103,7 +103,7 @@ int do_misaligned_access(unsigned long address, struct pt_regs *regs,
*/
void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
{
- die("Machine Check Exception", regs, address);
+ die("Unhandled Machine Check Exception", regs, address);
}
diff --git a/arch/arc/kernel/troubleshoot.c b/arch/arc/kernel/troubleshoot.c
index f9caf79186d4..7e94476f3994 100644
--- a/arch/arc/kernel/troubleshoot.c
+++ b/arch/arc/kernel/troubleshoot.c
@@ -140,7 +140,7 @@ static void show_ecr_verbose(struct pt_regs *regs)
} else if (vec == ECR_V_ITLB_MISS) {
pr_cont("Insn could not be fetched\n");
} else if (vec == ECR_V_MACH_CHK) {
- pr_cont("%s\n", (cause_code == 0x0) ?
+ pr_cont("Machine Check (%s)\n", (cause_code == 0x0) ?
"Double Fault" : "Other Fatal Err");
} else if (vec == ECR_V_PROTV) {
@@ -233,6 +233,9 @@ void show_kernel_fault_diag(const char *str, struct pt_regs *regs,
{
current->thread.fault_address = address;
+ /* Show fault description */
+ pr_info("\n%s\n", str);
+
/* Caller and Callee regs */
show_regs(regs);