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| author | Vineet Gupta <vgupta@synopsys.com> | 2015-04-06 17:23:57 +0530 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2015-06-22 14:06:55 +0530 |
| commit | d1f317d8254413447bcd6b6adbde24a985d256c2 (patch) | |
| tree | 4b0ba3c3a5335e844edbf97403c12b88b04f69d5 /arch/arc/include | |
| parent | d7a512bfe0be3790bae8465b4cb6c1bbca03c616 (diff) | |
| download | linux-d1f317d8254413447bcd6b6adbde24a985d256c2.tar.bz2 | |
ARCv2: MMUv4: cache programming model changes
Caveats about cache flush on ARCv2 based cores
- dcache is PIPT so paddr is sufficient for cache maintenance ops (no
need to setup PTAG reg
- icache is still VIPT but only aliasing configs need PTAG setup
So basically this is departure from MMU-v3 which always need vaddr in
line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG,
IC_PTAG respectively.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include')
| -rw-r--r-- | arch/arc/include/asm/arcregs.h | 5 | ||||
| -rw-r--r-- | arch/arc/include/asm/cache.h | 3 |
2 files changed, 6 insertions, 2 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index bcb08cd52d38..070f58827a5c 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -17,6 +17,7 @@ #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */ #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */ #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */ +#define ARC_REG_SLC_BCR 0xce #define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */ #define ARC_REG_TIMERS_BCR 0x75 #define ARC_REG_AP_BCR 0x76 @@ -331,7 +332,7 @@ struct cpuinfo_arc_mmu { }; struct cpuinfo_arc_cache { - unsigned int sz_k:8, line_len:8, assoc:4, ver:4, alias:1, vipt:1, pad:6; + unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1; }; struct cpuinfo_arc_bpu { @@ -343,7 +344,7 @@ struct cpuinfo_arc_ccm { }; struct cpuinfo_arc { - struct cpuinfo_arc_cache icache, dcache; + struct cpuinfo_arc_cache icache, dcache, slc; struct cpuinfo_arc_mmu mmu; struct cpuinfo_arc_bpu bpu; struct bcr_identity core; diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 7861255da32d..e54977a7d006 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -82,4 +82,7 @@ extern void read_decode_cache_bcr(void); #define DC_CTRL_INV_MODE_FLUSH 0x40 #define DC_CTRL_FLUSH_STATUS 0x100 +/*System-level cache (L2 cache) related Auxiliary registers */ +#define ARC_REG_SLC_CFG 0x901 + #endif /* _ASM_CACHE_H */ |