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| author | Vineet Gupta <vgupta@synopsys.com> | 2015-04-06 17:23:57 +0530 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2015-06-22 14:06:55 +0530 |
| commit | d1f317d8254413447bcd6b6adbde24a985d256c2 (patch) | |
| tree | 4b0ba3c3a5335e844edbf97403c12b88b04f69d5 /README | |
| parent | d7a512bfe0be3790bae8465b4cb6c1bbca03c616 (diff) | |
| download | linux-d1f317d8254413447bcd6b6adbde24a985d256c2.tar.bz2 | |
ARCv2: MMUv4: cache programming model changes
Caveats about cache flush on ARCv2 based cores
- dcache is PIPT so paddr is sufficient for cache maintenance ops (no
need to setup PTAG reg
- icache is still VIPT but only aliasing configs need PTAG setup
So basically this is departure from MMU-v3 which always need vaddr in
line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG,
IC_PTAG respectively.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'README')
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