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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-07-18 12:26:59 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-07-18 12:26:59 -0700 |
| commit | 0570bc8b7c9b41deba6f61ac218922e7168ad648 (patch) | |
| tree | 1dacd7730772b0ac46b24b9c127c332ef525e014 /MAINTAINERS | |
| parent | 0e2a5b5bd9a6aaec85df347dd71432a1d2d10763 (diff) | |
| parent | 2d69fbf3d01a5b71e98137e2406d4087960c512e (diff) | |
| download | linux-0570bc8b7c9b41deba6f61ac218922e7168ad648.tar.bz2 | |
Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Paul Walmsley:
- Hugepage support
- "Image" header support for RISC-V kernel binaries, compatible with
the current ARM64 "Image" header
- Initial page table setup now split into two stages
- CONFIG_SOC support (starting with SiFive SoCs)
- Avoid reserving memory between RAM start and the kernel in
setup_bootmem()
- Enable high-res timers and dynamic tick in the RV64 defconfig
- Remove long-deprecated gate area stubs
- MAINTAINERS updates to switch to the newly-created shared RISC-V git
tree, and to fix a get_maintainers.pl issue for patches involving
SiFive E-mail addresses
Also, one integration fix to resolve a build problem introduced during
in the v5.3-rc1 merge window:
- Fix build break after macro-to-function conversion in
asm-generic/cacheflush.h
* tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: fix build break after macro-to-function conversion in generic cacheflush.h
RISC-V: Add an Image header that boot loader can parse.
RISC-V: Setup initial page tables in two stages
riscv: remove free_initrd_mem
riscv: ccache: Remove unused variable
riscv: Introduce huge page support for 32/64bit kernel
x86, arm64: Move ARCH_WANT_HUGE_PMD_SHARE config in arch/Kconfig
RISC-V: Fix memory reservation in setup_bootmem()
riscv: defconfig: enable SOC_SIFIVE
riscv: select SiFive platform drivers with SOC_SIFIVE
arch: riscv: add config option for building SiFive's SoC resource
riscv: Remove gate area stubs
MAINTAINERS: change the arch/riscv git tree to the new shared tree
MAINTAINERS: don't automatically patches involving SiFive to the linux-riscv list
RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERS
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index e50faa93e170..500cdb68ccbc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13720,7 +13720,7 @@ RISC-V ARCHITECTURE M: Palmer Dabbelt <palmer@sifive.com> M: Albert Ou <aou@eecs.berkeley.edu> L: linux-riscv@lists.infradead.org -T: git git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git S: Supported F: arch/riscv/ K: riscv @@ -14582,7 +14582,7 @@ M: Paul Walmsley <paul.walmsley@sifive.com> L: linux-riscv@lists.infradead.org T: git git://github.com/sifive/riscv-linux.git S: Supported -K: sifive +K: [^@]sifive N: sifive SIFIVE FU540 SYSTEM-ON-CHIP |