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authorStefan Agner <stefan@agner.ch>2016-12-08 14:54:31 -0800
committerThierry Reding <treding@nvidia.com>2017-01-26 10:57:18 +0100
commiteaeebffa90f35e0f92658249b0e5c49ddfa89915 (patch)
treed7fc3a84d0df5003c2bf02b5fe6c415a96758fe3 /Documentation
parente6c2f066d5ed5ba61d48d54b603698bad1c6a270 (diff)
downloadlinux-eaeebffa90f35e0f92658249b0e5c49ddfa89915.tar.bz2
drm/panel: simple: Specify bus width and flags for EDT displays
The display has a 18-Bit parallel LCD interface, require DE to be active high and data driven by the controller on falling pixel clock edge (display samples on rising edge). Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
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