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author | Juergen Gross <jgross@suse.com> | 2018-08-21 17:37:55 +0200 |
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committer | Boris Ostrovsky <boris.ostrovsky@oracle.com> | 2018-08-27 14:20:49 -0400 |
commit | b2d7a075a1ccef2fb321d595802190c8e9b39004 (patch) | |
tree | f7112d61f399f9ee0643237d279b0ce662c9e8b0 /Documentation | |
parent | f7c90c2aa4004808dff777ba6ae2c7294dd06851 (diff) | |
download | linux-b2d7a075a1ccef2fb321d595802190c8e9b39004.tar.bz2 |
x86/pae: use 64 bit atomic xchg function in native_ptep_get_and_clear
Using only 32-bit writes for the pte will result in an intermediate
L1TF vulnerable PTE. When running as a Xen PV guest this will at once
switch the guest to shadow mode resulting in a loss of performance.
Use arch_atomic64_xchg() instead which will perform the requested
operation atomically with all 64 bits.
Some performance considerations according to:
https://software.intel.com/sites/default/files/managed/ad/dc/Intel-Xeon-Scalable-Processor-throughput-latency.pdf
The main number should be the latency, as there is no tight loop around
native_ptep_get_and_clear().
"lock cmpxchg8b" has a latency of 20 cycles, while "lock xchg" (with a
memory operand) isn't mentioned in that document. "lock xadd" (with xadd
having 3 cycles less latency than xchg) has a latency of 11, so we can
assume a latency of 14 for "lock xchg".
Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Tested-by: Jason Andryuk <jandryuk@gmail.com>
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions