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| author | Pierre Yves MORDRET <pierre-yves.mordret@st.com> | 2018-03-13 17:42:05 +0100 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@intel.com> | 2018-04-04 11:49:36 +0530 |
| commit | 9df3bd5520038225ceb3927021e6ea811c000c5b (patch) | |
| tree | 218fd78c96a1d64503db268c16ce5646f9326921 /Documentation | |
| parent | 80a76952a5a5d2914a5c04d6f3a151348e5580a5 (diff) | |
| download | linux-9df3bd5520038225ceb3927021e6ea811c000c5b.tar.bz2 | |
dmaengine: stm32-dma: properly mask irq bits
A single register of the controller holds the information for four dma
channels.
The functions stm32_dma_irq_status() don't mask the relevant bits after
the shift, thus adjacent channel's status is also reported in the returned
value.
Fixed by masking the value before returning it.
Similarly, the function stm32_dma_irq_clear() don't mask the input value
before shifting it, thus an incorrect input value could disable the
interrupts of adjacent channels.
Fixed by masking the input value before using it.
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions