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authorRussell King <rmk+kernel@arm.linux.org.uk>2016-01-05 11:07:28 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2016-01-05 11:07:28 +0000
commit598bcc6ea6ec4032d2ace8b1b43d11b4708af072 (patch)
tree675a2b01617549b539a4dcb1aec7141798e1f324 /Documentation
parent0bed4b7aa02c06e05121875dc443295d55b9d91d (diff)
parente679660dbb8347f275fe5d83a5dd59c1fb6c8e63 (diff)
downloadlinux-598bcc6ea6ec4032d2ace8b1b43d11b4708af072.tar.bz2
Merge branches 'misc' and 'misc-rc6' into for-linus
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/l2c2x0.txt13
1 files changed, 9 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt
index 1c0435446ecc..fe0398c5c77b 100644
--- a/Documentation/devicetree/bindings/arm/l2c2x0.txt
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
@@ -68,12 +68,17 @@ Optional properties:
disable if zero.
- arm,prefetch-offset : Override prefetch offset value. Valid values are
0-7, 15, 23, and 31.
-- arm,shared-override : The default behavior of the pl310 cache controller with
- respect to the shareable attribute is to transform "normal memory
- non-cacheable transactions" into "cacheable no allocate" (for reads) or
- "write through no write allocate" (for writes).
+- arm,shared-override : The default behavior of the L220 or PL310 cache
+ controllers with respect to the shareable attribute is to transform "normal
+ memory non-cacheable transactions" into "cacheable no allocate" (for reads)
+ or "write through no write allocate" (for writes).
On systems where this may cause DMA buffer corruption, this property must be
specified to indicate that such transforms are precluded.
+- arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310).
+- arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310).
+- arm,outer-sync-disable : disable the outer sync operation on the L2 cache.
+ Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
+ will randomly hang unless outer sync operations are disabled.
- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1>
(forcibly enable), property absent (retain settings set by firmware)
- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),