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| author | Minghuan Lian <Minghuan.Lian@nxp.com> | 2017-07-05 14:59:02 +0800 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2017-08-31 16:19:39 +0100 |
| commit | fd100dab63ef634e1e0e8b5d9d6d4ba7df9be93f (patch) | |
| tree | f928d82b8007a5403c9a7ccbff2fcba7ebd4c288 /Documentation | |
| parent | 4dd5da65a39d9a0405304fdef0804afffece044b (diff) | |
| download | linux-fd100dab63ef634e1e0e8b5d9d6d4ba7df9be93f.tar.bz2 | |
irqchip/ls-scfg-msi: Add LS1043a v1.1 MSI support
A MSI controller of LS1043a v1.0 only includes one MSIR and
is assigned one GIC interrupt. In order to support affinity,
LS1043a v1.1 MSI is assigned 4 MSIRs and 4 GIC interrupts.
But the MSIR has the different offset and only supports 8 MSIs.
The bits between variable bit_start and bit_end in structure
ls_scfg_msir are used to show 8 MSI interrupts. msir_irqs and
msir_base are added to describe the difference of MSI between
LS1043a v1.1 and other SoCs.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt index dde455289c16..49ccabbfa6f3 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt @@ -7,6 +7,7 @@ Required properties: "fsl,ls1021a-msi" "fsl,ls1043a-msi" "fsl,ls1046a-msi" + "fsl,ls1043a-v1.1-msi" - msi-controller: indicates that this is a PCIe MSI controller node - reg: physical base address of the controller and length of memory mapped. - interrupts: an interrupt to the parent interrupt controller. |