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authorLinus Torvalds <torvalds@linux-foundation.org>2016-11-11 16:21:20 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2016-11-11 16:21:20 -0800
commit5c03b53cb7386a5a9ee16b50de4d77d5cd06a438 (patch)
tree97a39e3178b49adb3a892c9cdc713897fde2c709 /Documentation
parent015ed9433be2b476ec7e2e6a9a411a56e3b5b035 (diff)
parenta33547cc764ca994d27a8fcc5fc61fbf4b2f7361 (diff)
downloadlinux-5c03b53cb7386a5a9ee16b50de4d77d5cd06a438.tar.bz2
Merge tag 'pinctrl-v4.9-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij: "All is about drivers, no core business going on. - Fix a host of runtime problems with the Intel Cherryview driver: suspend/resume needs to be marshalled properly, and strange effects from BIOS interaction during suspend/resume need to be dealt with. - A single bit was being set wrong in the Aspeed driver. - Fix an iProc probe ordering fallout resulting from v4.9 refactorings for bus population. - Do not specify a default trigger in the ST Micro cascaded GPIO IRQ controller: the kernel will moan. - Make IRQs optional altogether on the STM32 driver, it turns out not all systems have them or want them. - Fix a re-probe bug in the i.MX driver, it will eventually crash if probed repeatedly, not good" * tag 'pinctrl-v4.9-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl-aspeed-g5: Never set SCU90[6] pinctrl: cherryview: Prevent possible interrupt storm on resume pinctrl: cherryview: Serialize register access in suspend/resume pinctrl: imx: reset group index on probe pinctrl: stm32: move gpio irqs binding to optional pinctrl: stm32: remove dependency with interrupt controller pinctrl: st: don't specify default interrupt trigger pinctrl: iproc: Fix iProc and NSP GPIO support
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt10
1 files changed, 5 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index f9753c416974..b24583aa34c3 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -14,11 +14,6 @@ Required properies:
- #size-cells : The value of this property must be 1
- ranges : defines mapping between pin controller node (parent) to
gpio-bank node (children).
- - interrupt-parent: phandle of the interrupt parent to which the external
- GPIO interrupts are forwarded to.
- - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
- which includes IRQ mux selection register, and the offset of the IRQ mux
- selection register.
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
@@ -37,6 +32,11 @@ Required properties:
Optional properties:
- reset: : Reference to the reset controller
+ - interrupt-parent: phandle of the interrupt parent to which the external
+ GPIO interrupts are forwarded to.
+ - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
+ which includes IRQ mux selection register, and the offset of the IRQ mux
+ selection register.
Example:
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>