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authorBjorn Helgaas <bhelgaas@google.com>2017-02-21 15:13:30 -0600
committerBjorn Helgaas <bhelgaas@google.com>2017-02-21 15:13:30 -0600
commitb2e6d3055d5545b97533d4e8376fa848639d9951 (patch)
treec7e0a3ecdb8ca6dc2e13283479884c6673286eb7 /Documentation
parent1a55761392b8a4703039614f3ef6275f88dad4c3 (diff)
parente7cd7ef58e1fedb09b16720919869a81d7a2b867 (diff)
downloadlinux-b2e6d3055d5545b97533d4e8376fa848639d9951.tar.bz2
Merge branch 'pci/host-exynos' into next
* pci/host-exynos: PCI: exynos: Support the PHY generic framework Documentation: binding: Modify the exynos5440 PCIe binding phy: phy-exynos-pcie: Add support for Exynos PCIe PHY Documentation: samsung-phy: Add exynos-pcie-phy binding PCI: exynos: Refactor to make it easier to support other SoCs PCI: exynos: Remove duplicated code PCI: exynos: Use the bitops BIT() macro to build bitmasks PCI: exynos: Remove unnecessary local variables PCI: exynos: Replace the *_blk/*_phy/*_elb accessors PCI: exynos: Rename all pointer names from "exynos_pcie" to "ep" Conflicts: drivers/pci/dwc/pci-exynos.c
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt29
-rw-r--r--Documentation/devicetree/bindings/phy/samsung-phy.txt17
2 files changed, 46 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
index 4f9d23d2ed67..7d3b09474657 100644
--- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
@@ -7,8 +7,19 @@ Required properties:
- compatible: "samsung,exynos5440-pcie"
- reg: base addresses and lengths of the pcie controller,
the phy controller, additional register for the phy controller.
+ (Registers for the phy controller are DEPRECATED.
+ Use the PHY framework.)
+- reg-names : First name should be set to "elbi".
+ And use the "config" instead of getting the confgiruation address space
+ from "ranges".
+ NOTE: When use the "config" property, reg-names must be set.
- interrupts: A list of interrupt outputs for level interrupt,
pulse interrupt, special interrupt.
+- phys: From PHY binding. Phandle for the Generic PHY.
+ Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
+
+Other common properties refer to
+ Documentation/devicetree/binding/pci/designware-pcie.txt
Example:
@@ -54,6 +65,24 @@ SoC specific DT Entry:
num-lanes = <4>;
};
+With using PHY framework:
+ pcie_phy0: pcie-phy@270000 {
+ ...
+ reg = <0x270000 0x1000>, <0x271000 0x40>;
+ reg-names = "phy", "block";
+ ...
+ };
+
+ pcie@290000 {
+ ...
+ reg = <0x290000 0x1000>, <0x40000000 0x1000>;
+ reg-names = "elbi", "config";
+ phys = <&pcie_phy0>;
+ ranges = <0x81000000 0 0 0x60001000 0 0x00010000
+ 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
+ ...
+ };
+
Board specific DT Entry:
pcie@290000 {
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 9872ba8546bd..ab80bfe31cb3 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -191,3 +191,20 @@ Example:
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
+
+Samsung Exynos SoC series PCIe PHY controller
+--------------------------------------------------
+Required properties:
+- compatible : Should be set to "samsung,exynos5440-pcie-phy"
+- #phy-cells : Must be zero
+- reg : a register used by phy driver.
+ - First is for phy register, second is for block register.
+- reg-names : Must be set to "phy" and "block".
+
+Example:
+ pcie_phy0: pcie-phy@270000 {
+ #phy-cells = <0>;
+ compatible = "samsung,exynos5440-pcie-phy";
+ reg = <0x270000 0x1000>, <0x271000 0x40>;
+ reg-names = "phy", "block";
+ };