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authorBjorn Helgaas <bhelgaas@google.com>2020-04-02 14:27:01 -0500
committerBjorn Helgaas <bhelgaas@google.com>2020-04-02 14:27:01 -0500
commitd09fca9ecddb675d0c52499a729a687a22a77443 (patch)
tree2081d8acf5be0e9fd50b38bc863f4adb52dca4bc /Documentation
parenta29a44c197114a9b9559f547f826cf282f00a755 (diff)
parent863bba34d2f4c189a851643712cfc341ef7bcb8f (diff)
downloadlinux-d09fca9ecddb675d0c52499a729a687a22a77443.tar.bz2
Merge branch 'remotes/lorenzo/pci/mobiveil'
- Restructure mobiveil driver to support either Root Complex mode or Endpoint mode (Hou Zhiqiang) - Collect host initialization into one place (Hou Zhiqiang) - Collect interrupt-related code into one place (Hou Zhiqiang) - Split mobiveil into separate files under drivers/pci/controller/mobiveil for easier reuse (Hou Zhiqiang) - Add callbacks for interrupt initialization and linkup checking (Hou Zhiqiang) - Add 8- and 16-bit CSR accessors (Hou Zhiqiang) - Initialize host driver only if Header Type is "bridge" (Hou Zhiqiang) - Add DT bindings for NXP Layerscape SoCs PCIe Gen4 controller (Hou Zhiqiang) - Add PCIe Gen4 RC driver for Layerscape SoCs (Hou Zhiqiang) - Add pcie-mobiveil __iomem annotations (Hou Zhiqiang) - Add PCI_MSI_IRQ_DOMAIN Kconfig dependency (Hou Zhiqiang) * remotes/lorenzo/pci/mobiveil: PCI: mobiveil: Fix unmet dependency warning for PCIE_MOBIVEIL_PLAT PCI: mobiveil: Fix sparse different address space warnings PCI: mobiveil: Add PCIe Gen4 RC driver for Layerscape SoCs dt-bindings: PCI: Add NXP Layerscape SoCs PCIe Gen4 controller PCI: mobiveil: Add Header Type field check PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors PCI: mobiveil: Allow mobiveil_host_init() to be used to re-init host PCI: mobiveil: Add callback function for link up check PCI: mobiveil: Add callback function for interrupt initialization PCI: mobiveil: Modularize the Mobiveil PCIe Host Bridge IP driver PCI: mobiveil: Collect the interrupt related operations into a function PCI: mobiveil: Move the host initialization into a function PCI: mobiveil: Introduce a new structure mobiveil_root_port
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt52
1 files changed, 52 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
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index 000000000000..b40fb5d15d3d
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+++ b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
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+NXP Layerscape PCIe Gen4 controller
+
+This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
+the common properties defined in mobiveil-pcie.txt.
+
+Required properties:
+- compatible: should contain the platform identifier such as:
+ "fsl,lx2160a-pcie"
+- reg: base addresses and lengths of the PCIe controller register blocks.
+ "csr_axi_slave": Bridge config registers
+ "config_axi_slave": PCIe controller registers
+- interrupts: A list of interrupt outputs of the controller. Must contain an
+ entry for each entry in the interrupt-names property.
+- interrupt-names: It could include the following entries:
+ "intr": The interrupt that is asserted for controller interrupts
+ "aer": Asserted for aer interrupt when chip support the aer interrupt with
+ none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
+ "pme": Asserted for pme interrupt when chip support the pme interrupt with
+ none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
+- dma-coherent: Indicates that the hardware IP block can ensure the coherency
+ of the data transferred from/to the IP block. This can avoid the software
+ cache flush/invalid actions, and improve the performance significantly.
+- msi-parent : See the generic MSI binding described in
+ Documentation/devicetree/bindings/interrupt-controller/msi.txt.
+
+Example:
+
+ pcie@3400000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x80 0x00000000 0x0 0x00001000>; /* configuration space */
+ reg-names = "csr_axi_slave", "config_axi_slave";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "aer", "pme", "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ msi-parent = <&its>;
+ ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ };