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authorLinus Torvalds <torvalds@linux-foundation.org>2014-07-13 12:10:18 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2014-07-13 12:10:18 -0700
commit2f3870e9e8600cd34030e622fea4bc236f855c24 (patch)
tree1b1ec6e5dc28cad6a2727acf06fdfec6fcdea7a8 /Documentation
parent5fa77b54eff1e4fb38494b5a24c66768d6e7c148 (diff)
parentcacadb4ff969a82628d47db87b5a531be466b134 (diff)
downloadlinux-2f3870e9e8600cd34030e622fea4bc236f855c24.tar.bz2
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson: "This week's arm-soc fixes: - Another set of OMAP fixes * Clock fixes * Restart handling * PHY regulators * SATA hwmod data for DRA7 + Some trivial fixes and removal of a bit of dead code - Exynos fixes * A bunch of clock fixes * Some SMP fixes * Exynos multi-core timer: register as clocksource and fix ftrace. + a few other minor fixes There's also a couple more patches, and at91 fix for USB caused by common clock conversion, and more MAINTAINERS entries for shmobile. We're definitely switching to only regression fixes from here on out, we've been a little less strict than usual up until now" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits) ARM: at91: at91sam9x5: add clocks for usb device ARM: EXYNOS: Register cpuidle device only on exynos4210 and 5250 ARM: dts: Add clock property for mfc_pd in exynos5420 clk: exynos5420: Add IDs for clocks used in PD mfc ARM: EXYNOS: Add support for clock handling in power domain ARM: OMAP2+: Remove non working OMAP HDMI audio initialization ARM: imx: fix shared gate clock ARM: dts: Update the parent for Audss clocks in Exynos5420 ARM: EXYNOS: Update secondary boot addr for secure mode ARM: dts: Fix TI CPSW Phy mode selection on IGEP COM AQUILA. ARM: dts: am335x-evmsk: Enable the McASP FIFO for audio ARM: dts: am335x-evm: Enable the McASP FIFO for audio ARM: OMAP2+: Make GPMC skip disabled devices ARM: OMAP2+: create dsp device only on OMAP3 SoCs ARM: dts: dra7-evm: Make VDDA_1V8_PHY supply always on ARM: DRA7/AM43XX: fix header definition for omap44xx_restart ARM: OMAP2+: clock/dpll: fix _dpll_test_fint arithmetics overflow ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss ARM: DRA7: hwmod: Fixup SATA hwmod ARM: OMAP3: PRM/CM: Add back macros used by TI DSP/Bridge driver ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/exynos/power_domain.txt20
1 files changed, 20 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 5216b419016a..8b4f7b7fe88b 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -9,6 +9,18 @@ Required Properties:
- reg: physical base address of the controller and length of memory mapped
region.
+Optional Properties:
+- clocks: List of clock handles. The parent clocks of the input clocks to the
+ devices in this power domain are set to oscclk before power gating
+ and restored back after powering on a domain. This is required for
+ all domains which are powered on and off and not required for unused
+ domains.
+- clock-names: The following clocks can be specified:
+ - oscclk: Oscillator clock.
+ - pclkN, clkN: Pairs of parent of input clock and input clock to the
+ devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
+ are supported currently.
+
Node of a device using power domains must have a samsung,power-domain property
defined with a phandle to respective power domain.
@@ -19,6 +31,14 @@ Example:
reg = <0x10023C00 0x10>;
};
+ mfc_pd: power-domain@10044060 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10044060 0x20>;
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
+ <&clock CLK_MOUT_USER_ACLK333>;
+ clock-names = "oscclk", "pclk0", "clk0";
+ };
+
Example of the node using power domain:
node {