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| author | Reinette Chatre <reinette.chatre@intel.com> | 2018-06-22 15:42:29 -0700 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-06-24 15:35:48 +0200 |
| commit | f3be1e7b2cf8bc096386a3588fc640b0db6b28d7 (patch) | |
| tree | 28024ec800ab578d0c5419706f805723d2ca3fc3 /Documentation/x86 | |
| parent | 8a2fc0e1bc0cd856101927188884d7c370b62188 (diff) | |
| download | linux-f3be1e7b2cf8bc096386a3588fc640b0db6b28d7.tar.bz2 | |
x86/intel_rdt: Support L3 cache performance event of Broadwell
Broadwell microarchitecture supports pseudo-locking. Add support for
the L3 cache related performance events of these systems so that
the success of pseudo-locking can be measured more accurately on these
platforms.
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: fenghua.yu@intel.com
Cc: tony.luck@intel.com
Cc: vikas.shivappa@linux.intel.com
Cc: gavin.hindman@intel.com
Cc: jithu.joseph@intel.com
Cc: dave.hansen@intel.com
Cc: hpa@zytor.com
Link: https://lkml.kernel.org/r/36c1414e9bd17c3faf440f32b644b9c879bcbae2.1529706536.git.reinette.chatre@intel.com
Diffstat (limited to 'Documentation/x86')
0 files changed, 0 insertions, 0 deletions