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author | Michael Shych <michaelsh@mellanox.com> | 2018-03-27 14:01:26 +0000 |
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committer | Wolfram Sang <wsa@the-dreams.de> | 2018-04-30 10:39:29 +0200 |
commit | 27aaa8ad5a5e79d01653523c305fe6af707dce8e (patch) | |
tree | 8cebaa371cbea71f557ed6767ed0e66c42f0642b /Documentation/i2c | |
parent | ae4aa68dd3e4bf16bff6078c1851b832b0b3db1a (diff) | |
download | linux-27aaa8ad5a5e79d01653523c305fe6af707dce8e.tar.bz2 |
i2c: mlxcpld: Add capability register description to documentation
It adds capability register description to documentation.
Signed-off-by: Michael Shych <michaelsh@mellanox.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'Documentation/i2c')
-rw-r--r-- | Documentation/i2c/busses/i2c-mlxcpld | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/i2c/busses/i2c-mlxcpld b/Documentation/i2c/busses/i2c-mlxcpld index 4e46c440b38d..925904aa9b57 100644 --- a/Documentation/i2c/busses/i2c-mlxcpld +++ b/Documentation/i2c/busses/i2c-mlxcpld @@ -20,6 +20,10 @@ The next transaction types are supported: - Write Byte/Block. Registers: +CPBLTY 0x0 - capability reg. + Bits [6:5] - transaction length. b01 - 72B is supported, + 36B in other case. + Bit 7 - SMBus block read support. CTRL 0x1 - control reg. Resets all the registers. HALF_CYC 0x4 - cycle reg. |