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authorRalf Baechle <ralf@linux-mips.org>2012-10-05 15:56:28 +0200
committerRalf Baechle <ralf@linux-mips.org>2012-10-05 15:56:28 +0200
commit382fc33b4a04e2dde89b4c69a6880e0c7d9761e2 (patch)
tree9d13ef333c4e841756c45bf29600ceac28e3f85e /Documentation/devicetree
parent97541ccfb9db2bb9cd1dde6344d5834438d14bda (diff)
parent986936d7c2f83427bb3bf1e629eba4373438e151 (diff)
downloadlinux-382fc33b4a04e2dde89b4c69a6880e0c7d9761e2.tar.bz2
Merge branch 'master' of git://dev.phrozen.org/mips-next into mips-for-linux-next
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/spi/spi-octeon.txt33
1 files changed, 33 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-octeon.txt b/Documentation/devicetree/bindings/spi/spi-octeon.txt
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index 000000000000..431add192342
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+++ b/Documentation/devicetree/bindings/spi/spi-octeon.txt
@@ -0,0 +1,33 @@
+Cavium, Inc. OCTEON SOC SPI master controller.
+
+Required properties:
+- compatible : "cavium,octeon-3010-spi"
+- reg : The register base for the controller.
+- interrupts : One interrupt, used by the controller.
+- #address-cells : <1>, as required by generic SPI binding.
+- #size-cells : <0>, also as required by generic SPI binding.
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+ spi@1070000001000 {
+ compatible = "cavium,octeon-3010-spi";
+ reg = <0x10700 0x00001000 0x0 0x100>;
+ interrupts = <0 58>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ compatible = "st,m95256", "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ spi-cpha;
+ spi-cpol;
+
+ pagesize = <64>;
+ size = <32768>;
+ address-width = <16>;
+ };
+ };
+