Merge tag 'mtd/for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

Pull MTD updates from Miquel Raynal:
 "MTD core:
   - Fix refcounting for unpartitioned MTDs
   - Fix misspelled function parameter 'section'
   - Remove unneeded break
   - cmdline parser: Fix parsing of part-names with colons
   - mtdpart: Fix misdocumented function parameter 'mtd'

  MTD devices:
   - phram:
      - Allow the user to set the erase page size
      - File headers are not good candidates for kernel-doc
   - physmap-bt1-rom: Fix __iomem addrspace removal warning
   - plat-ram: correctly free memory on error path in platram_probe()
   - powernv_flash: Add function names to headers and fix 'dev'
   - docg3: Fix kernel-doc 'bad line' and 'excessive doc' issues

  UBI cleanup fixes:
   - gluebi: Fix misnamed function parameter documentation
   - wl: Fix a couple of kernel-doc issues
   - eba: Fix a couple of misdocumentation issues
   - kapi: Correct documentation for 'ubi_leb_read_sg's 'sgl' parameter
   - Document 'ubi_num' in struct mtd_dev_param

  Generic NAND core ECC management:
   - Add an I/O request tweaking mechanism
   - Entire rework of the software BCH ECC driver, creation of a real
     ECC engine, getting rid of raw NAND structures, migration to more
     generic prototypes, misc fixes and style cleanup. Moved now to the
     Generic NAND layer.
   - Entire rework of the software Hamming ECC driver, creation of a
     real ECC engine, getting rid of raw NAND structures, misc renames,
     comment updates, cleanup, and style fixes. Moved now to the generic
     NAND layer.
   - Necessary plumbing at the NAND level to retrieve generic NAND ECC
     engines (softwares and on-die).
   - Update of the bindings.

  Raw NAND core:
   - Geting rid of the chip->ecc.priv entry.
   - Fix miscellaneous typos in kernel-doc

  Raw NAND controller drivers:
   - Arasan: Document 'anfc_op's 'buf' member
   - AU1550: Ensure the presence of the right includes
   - Brcmnand: Demote non-conformant kernel-doc headers
   - Cafe: Remove superfluous param doc and add another
   - Davinci: Do not use extra dereferencing
   - Diskonchip: Marking unused variables as __always_unused
   - GPMI:
      - Fix the driver only sense CS0 R/B issue
      - Fix the random DMA timeout issue
      - Use a single line for of_device_id
      - Use of_device_get_match_data()
      - Fix reference count leak in gpmi ops
      - Cleanup makefile
      - Fix binding matching of clocks on different SoCs
   - Ingenic: remove redundant get_device() in ingenic_ecc_get()
   - Intel LGM: New NAND controller driver
   - Marvell: Drop useless line
   - Meson:
      - Fix a resource leak in init
      - Fix meson_nfc_dma_buffer_release() arguments
   - mxc:
      - Use device_get_match_data()
      - Use a single line for of_device_id
      - Remove platform data support
   - Omap:
      - Fix a bunch of kernel-doc misdemeanours
      - Finish ELM half populated function header, demote empty ones
   - s3c2410: Add documentation for 2 missing struct members
   - Sunxi: Document 'sunxi_nfc's 'caps' member
   - Qcom:
      - Add support for SDX55
      - Support for IPQ6018 QPIC NAND controller
      - Fix DMA sync on FLASH_STATUS register read
   - Rockchip: New NAND controller driver for RK3308, RK2928 and others
   - Sunxi: Add MDMA support

  ONENAND:
   - bbt: Fix expected kernel-doc formatting
   - Fix some kernel-doc misdemeanours
   - Fix expected kernel-doc formatting
   - Use mtd->oops_panic_write as condition

  SPI-NAND core:
   - Creation of a SPI-NAND on-die ECC engine
   - Move ECC related definitions earlier in the driver
   - Fix typo in comment
   - Fill a default ECC provider/algorithm
   - Remove outdated comment
   - Fix OOB read
   - Allow the case where there is no ECC engine
   - Use the external ECC engine logic

  SPI-NAND chip drivers:
   - Micron:
      - Add support for MT29F2G01AAAED
      - Use more specific names
   - Macronix:
      - Add support for MX35LFxG24AD
      - Add support for MX35LFxGE4AD
   - Toshiba: Demote non-conformant kernel-doc header

  SPI-NOR core:
   - Initial support for stateful Octal DTR mode using volatile settings
   - Preliminary support for JEDEC 251 (xSPI) and JEDEC 216D standards
   - Support for Cypress Semper flash
   - Support to specify ECC block size of SPI NOR flashes
   - Fixes to avoid clearing of non-volatile Block Protection bits at
     probe
   - hisi-sfc: Demote non-conformant kernel-doc"

* tag 'mtd/for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (120 commits)
  mtd: spinand: macronix: Add support for MX35LFxG24AD
  mtd: rawnand: rockchip: NFC driver for RK3308, RK2928 and others
  dt-bindings: mtd: Describe Rockchip RK3xxx NAND flash controller
  mtd: rawnand: gpmi: Use a single line for of_device_id
  mtd: rawnand: gpmi: Fix the random DMA timeout issue
  mtd: rawnand: gpmi: Fix the driver only sense CS0 R/B issue
  mtd: rawnand: qcom: Add NAND controller support for SDX55
  dt-bindings: qcom_nandc: Add SDX55 QPIC NAND documentation
  mtd: rawnand: mxc: Use a single line for of_device_id
  mtd: rawnand: mxc: Use device_get_match_data()
  mtd: rawnand: meson: Fix a resource leak in init
  mtd: rawnand: gpmi: Use of_device_get_match_data()
  mtd: rawnand: Add NAND controller support on Intel LGM SoC
  dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC
  mtd: spinand: micron: Add support for MT29F2G01AAAED
  mtd: spinand: micron: Use more specific names
  mtd: rawnand: gpmi: fix reference count leak in gpmi ops
  dt-bindings: mtd: gpmi-nand: Fix matching of clocks on different SoCs
  mtd: spinand: macronix: Add support for MX35LFxGE4AD
  mtd: plat-ram: correctly free memory on error path in platram_probe()
  ...

5 files changed, 326 insertions, 25 deletions

diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml b/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml
index 28ff8c581837..9d764e654e1d 100644
--- a/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml
+++ b/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml
@@ -9,9 +9,6 @@ title: Freescale General-Purpose Media Interface (GPMI) binding
 maintainers:
   - Han Xu <han.xu@nxp.com>
 
-allOf:
-  - $ref: "nand-controller.yaml"
-
 description: |
   The GPMI nand controller provides an interface to control the NAND
   flash chips. The device tree may optionally contain sub-nodes
@@ -58,22 +55,10 @@ properties:
   clocks:
     minItems: 1
     maxItems: 5
-    items:
-      - description: SoC gpmi io clock
-      - description: SoC gpmi apb clock
-      - description: SoC gpmi bch clock
-      - description: SoC gpmi bch apb clock
-      - description: SoC per1 bch clock
 
   clock-names:
     minItems: 1
     maxItems: 5
-    items:
-      - const: gpmi_io
-      - const: gpmi_apb
-      - const: gpmi_bch
-      - const: gpmi_bch_apb
-      - const: per1_bch
 
   fsl,use-minimum-ecc:
     type: boolean
@@ -107,6 +92,67 @@ required:
 
 unevaluatedProperties: false
 
+allOf:
+  - $ref: "nand-controller.yaml"
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - fsl,imx23-gpmi-nand
+              - fsl,imx28-gpmi-nand
+    then:
+      properties:
+        clocks:
+          items:
+            - description: SoC gpmi io clock
+        clock-names:
+          items:
+            - const: gpmi_io
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - fsl,imx6q-gpmi-nand
+              - fsl,imx6sx-gpmi-nand
+    then:
+      properties:
+        clocks:
+          items:
+            - description: SoC gpmi io clock
+            - description: SoC gpmi apb clock
+            - description: SoC gpmi bch clock
+            - description: SoC gpmi bch apb clock
+            - description: SoC per1 bch clock
+        clock-names:
+          items:
+            - const: gpmi_io
+            - const: gpmi_apb
+            - const: gpmi_bch
+            - const: gpmi_bch_apb
+            - const: per1_bch
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: fsl,imx7d-gpmi-nand
+    then:
+      properties:
+        clocks:
+          items:
+            - description: SoC gpmi io clock
+            - description: SoC gpmi bch apb clock
+        clock-names:
+          minItems: 2
+          maxItems: 2
+          items:
+            - const: gpmi_io
+            - const: gpmi_bch_apb
+
 examples:
   - |
     nand-controller@8000c000 {
diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
new file mode 100644
index 000000000000..30e0c66ab0eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel LGM SoC NAND Controller Device Tree Bindings
+
+allOf:
+  - $ref: "nand-controller.yaml"
+
+maintainers:
+  - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
+
+properties:
+  compatible:
+    const: intel,lgm-nand
+
+  reg:
+    maxItems: 6
+
+  reg-names:
+    items:
+      - const: ebunand
+      - const: hsnand
+      - const: nand_cs0
+      - const: nand_cs1
+      - const: addr_sel0
+      - const: addr_sel1
+
+  clocks:
+    maxItems: 1
+
+  dmas:
+    maxItems: 2
+
+  dma-names:
+    items:
+      - const: tx
+      - const: rx
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "^nand@[a-f0-9]+$":
+    type: object
+    properties:
+      reg:
+        minimum: 0
+        maximum: 7
+
+      nand-ecc-mode: true
+
+      nand-ecc-algo:
+        const: hw
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - dmas
+  - dma-names
+  - "#address-cells"
+  - "#size-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    nand-controller@e0f00000 {
+      compatible = "intel,lgm-nand";
+      reg = <0xe0f00000 0x100>,
+            <0xe1000000 0x300>,
+            <0xe1400000 0x8000>,
+            <0xe1c00000 0x1000>,
+            <0x17400000 0x4>,
+            <0x17c00000 0x4>;
+      reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1",
+        "addr_sel0", "addr_sel1";
+      clocks = <&cgu0 125>;
+      dmas = <&dma0 8>, <&dma0 9>;
+      dma-names = "tx", "rx";
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      nand@0 {
+        reg = <0>;
+        nand-ecc-mode = "hw";
+      };
+    };
+
+...
diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
index b29050fd7470..d0e422f4b3e0 100644
--- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml
+++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
@@ -46,15 +46,6 @@ patternProperties:
         description:
           Contains the native Ready/Busy IDs.
 
-      nand-ecc-mode:
-        description:
-          Desired ECC engine, either hardware (most of the time
-          embedded in the NAND controller) or software correction
-          (Linux will handle the calculations). soft_bch is deprecated
-          and should be replaced by soft and nand-ecc-algo.
-        $ref: /schemas/types.yaml#/definitions/string
-        enum: [none, soft, hw, hw_syndrome, hw_oob_first, on-die]
-
       nand-ecc-engine:
         allOf:
           - $ref: /schemas/types.yaml#/definitions/phandle
@@ -171,7 +162,7 @@ examples:
 
       nand@0 {
         reg = <0>;
-        nand-ecc-mode = "soft";
+        nand-use-soft-ecc-engine;
         nand-ecc-algo = "bch";
 
         /* controller specific properties */
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index 5c2fba4b30fe..5647913d8837 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -6,8 +6,12 @@ Required properties:
 			    SoC and it uses ADM DMA
     * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
                             IPQ4019 SoC and it uses BAM DMA
+    * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in
+                            IPQ6018 SoC and it uses BAM DMA
     * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
                             IPQ8074 SoC and it uses BAM DMA
+    * "qcom,sdx55-nand"   - for QPIC NAND controller v2.0.0 being used in
+                            SDX55 SoC and it uses BAM DMA
 
 - reg:			MMIO address range
 - clocks:		must contain core clock and always on clock
diff --git a/Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml
new file mode 100644
index 000000000000..0922536b1811
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml
@@ -0,0 +1,161 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoCs NAND FLASH Controller (NFC)
+
+allOf:
+  - $ref: "nand-controller.yaml#"
+
+maintainers:
+  - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+  compatible:
+    oneOf:
+      - const: rockchip,px30-nfc
+      - const: rockchip,rk2928-nfc
+      - const: rockchip,rv1108-nfc
+      - items:
+          - const: rockchip,rk3036-nfc
+          - const: rockchip,rk2928-nfc
+      - items:
+          - const: rockchip,rk3308-nfc
+          - const: rockchip,rv1108-nfc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    items:
+      - description: Bus Clock
+      - description: Module Clock
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: ahb
+      - const: nfc
+
+  assigned-clocks:
+    maxItems: 1
+
+  assigned-clock-rates:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+patternProperties:
+  "^nand@[0-7]$":
+    type: object
+    properties:
+      reg:
+        minimum: 0
+        maximum: 7
+
+      nand-ecc-mode:
+        const: hw
+
+      nand-ecc-step-size:
+        const: 1024
+
+      nand-ecc-strength:
+        enum: [16, 24, 40, 60, 70]
+        description: |
+          The ECC configurations that can be supported are as follows.
+            NFC v600 ECC 16, 24, 40, 60
+              RK2928, RK3066, RK3188
+
+            NFC v622 ECC 16, 24, 40, 60
+              RK3036, RK3128
+
+            NFC v800 ECC 16
+              RK3308, RV1108
+
+            NFC v900 ECC 16, 40, 60, 70
+              RK3326, PX30
+
+      nand-bus-width:
+        const: 8
+
+      rockchip,boot-blks:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        minimum: 2
+        default: 16
+        description:
+          The NFC driver need this information to select ECC
+          algorithms supported by the boot ROM.
+          Only used in combination with 'nand-is-boot-medium'.
+
+      rockchip,boot-ecc-strength:
+        enum: [16, 24, 40, 60, 70]
+        allOf:
+          - $ref: /schemas/types.yaml#/definitions/uint32
+        description: |
+          If specified it indicates that a different BCH/ECC setting is
+          supported by the boot ROM.
+            NFC v600 ECC 16, 24
+              RK2928, RK3066, RK3188
+
+            NFC v622 ECC 16, 24, 40, 60
+              RK3036, RK3128
+
+            NFC v800 ECC 16
+              RK3308, RV1108
+
+            NFC v900 ECC 16, 70
+              RK3326, PX30
+
+          Only used in combination with 'nand-is-boot-medium'.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/rk3308-cru.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    nfc: nand-controller@ff4b0000 {
+      compatible = "rockchip,rk3308-nfc",
+                   "rockchip,rv1108-nfc";
+      reg = <0xff4b0000 0x4000>;
+      interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+      clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
+      clock-names = "ahb", "nfc";
+      assigned-clocks = <&clks SCLK_NANDC>;
+      assigned-clock-rates = <150000000>;
+
+      pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
+                   &flash_rdn &flash_rdy &flash_wrn>;
+      pinctrl-names = "default";
+
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      nand@0 {
+        reg = <0>;
+        label = "rk-nand";
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        nand-ecc-step-size = <1024>;
+        nand-ecc-strength = <16>;
+        nand-is-boot-medium;
+        rockchip,boot-blks = <8>;
+        rockchip,boot-ecc-strength = <16>;
+      };
+    };
+
+...