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author | Bjorn Helgaas <bhelgaas@google.com> | 2020-04-02 14:26:50 -0500 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2020-04-02 14:26:50 -0500 |
commit | 86d0b6a131052b6b98ebda5a65c03a9f89914316 (patch) | |
tree | ca4af42948a5f35fb8a56b63fded4591197887e5 /Documentation/devicetree/bindings/pci | |
parent | d620d86426bab7b01150c961e9c0cee0ac24c5b6 (diff) | |
parent | 11be8af70d86c0a03706b329fb6f1a7329e3343a (diff) | |
download | linux-86d0b6a131052b6b98ebda5a65c03a9f89914316.tar.bz2 |
Merge branch 'remotes/lorenzo/pci/dt'
- Add common schema for PCI endpoint controllers (Kishon Vijay Abraham I)
- Add host and endpoint schemas for Cadence PCIe core (Kishon Vijay
Abraham I)
- Convert Cadence platform bindings to DT schema (Kishon Vijay Abraham I)
* remotes/lorenzo/pci/dt:
dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema
dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe
dt-bindings: PCI: Add PCI Endpoint Controller Schema
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
7 files changed, 224 insertions, 93 deletions
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt deleted file mode 100644 index 4a0475e2ba7e..000000000000 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Cadence PCIe endpoint controller - -Required properties: -- compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used. -- reg: Should contain the controller register base address and AXI interface - region base address respectively. -- reg-names: Must be "reg" and "mem" respectively. -- cdns,max-outbound-regions: Set to maximum number of outbound regions - -Optional properties: -- max-functions: Maximum number of functions that can be configured (default 1). -- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more - than one in the list. If only one PHY listed it must manage all lanes. -- phy-names: List of names to identify the PHY. - -Example: - -pcie@fc000000 { - compatible = "cdns,cdns-pcie-ep"; - reg = <0x0 0xfc000000 0x0 0x01000000>, - <0x0 0x80000000 0x0 0x40000000>; - reg-names = "reg", "mem"; - cdns,max-outbound-regions = <16>; - max-functions = /bits/ 8 <8>; - phys = <&ep_phy0 &ep_phy1>; - phy-names = "pcie-lane0","pcie-lane1"; -}; diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml new file mode 100644 index 000000000000..2996f8d4777c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence PCIe EP Controller + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +allOf: + - $ref: "cdns-pcie.yaml#" + - $ref: "pci-ep.yaml#" + +properties: + compatible: + const: cdns,cdns-pcie-ep + + reg: + maxItems: 2 + + reg-names: + items: + - const: reg + - const: mem + +required: + - reg + - reg-names + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie-ep@fc000000 { + compatible = "cdns,cdns-pcie-ep"; + reg = <0x0 0xfc000000 0x0 0x01000000>, + <0x0 0x80000000 0x0 0x40000000>; + reg-names = "reg", "mem"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <8>; + phys = <&pcie_phy0>; + phy-names = "pcie-phy"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt deleted file mode 100644 index 91de69c713a9..000000000000 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt +++ /dev/null @@ -1,66 +0,0 @@ -* Cadence PCIe host controller - -This PCIe controller inherits the base properties defined in -host-generic-pci.txt. - -Required properties: -- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used. -- reg: Should contain the controller register base address, PCIe configuration - window base address, and AXI interface region base address respectively. -- reg-names: Must be "reg", "cfg" and "mem" respectively. -- #address-cells: Set to <3> -- #size-cells: Set to <2> -- device_type: Set to "pci" -- ranges: Ranges for the PCI memory and I/O regions -- #interrupt-cells: Set to <1> -- interrupt-map-mask and interrupt-map: Standard PCI properties to define the - mapping of the PCIe interface to interrupt numbers. - -Optional properties: -- cdns,max-outbound-regions: Set to maximum number of outbound regions - (default 32) -- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the - number of least significant bits kept during inbound (PCIe -> AXI) address - translations (default 32) -- vendor-id: The PCI vendor ID (16 bits, default is design dependent) -- device-id: The PCI device ID (16 bits, default is design dependent) -- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more - than one in the list. If only one PHY listed it must manage all lanes. -- phy-names: List of names to identify the PHY. - -Example: - -pcie@fb000000 { - compatible = "cdns,cdns-pcie-host"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - linux,pci-domain = <0>; - cdns,max-outbound-regions = <16>; - cdns,no-bar-match-nbits = <32>; - vendor-id = /bits/ 16 <0x17cd>; - device-id = /bits/ 16 <0x0200>; - - reg = <0x0 0xfb000000 0x0 0x01000000>, - <0x0 0x41000000 0x0 0x00001000>, - <0x0 0x40000000 0x0 0x04000000>; - reg-names = "reg", "cfg", "mem"; - - ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, - <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; - - #interrupt-cells = <0x1>; - - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; - - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - - msi-parent = <&its_pci>; - - phys = <&pcie_phy0>; - phy-names = "pcie-phy"; -}; diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml new file mode 100644 index 000000000000..cabbe46ff578 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence PCIe host controller + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: "cdns-pcie-host.yaml#" + +properties: + compatible: + const: cdns,cdns-pcie-host + + reg: + maxItems: 3 + + reg-names: + items: + - const: reg + - const: cfg + - const: mem + + msi-parent: true + +required: + - reg + - reg-names + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie@fb000000 { + compatible = "cdns,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + linux,pci-domain = <0>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <32>; + vendor-id = <0x17cd>; + device-id = <0x0200>; + + reg = <0x0 0xfb000000 0x0 0x01000000>, + <0x0 0x41000000 0x0 0x00001000>, + <0x0 0x40000000 0x0 0x04000000>; + reg-names = "reg", "cfg", "mem"; + + ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, + <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; + + #interrupt-cells = <0x1>; + + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1>, + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1>, + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1>, + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; + + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + + msi-parent = <&its_pci>; + + phys = <&pcie_phy0>; + phy-names = "pcie-phy"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml new file mode 100644 index 000000000000..ab6e43b636ec --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence PCIe Host + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +allOf: + - $ref: "/schemas/pci/pci-bus.yaml#" + - $ref: "cdns-pcie.yaml#" + +properties: + cdns,no-bar-match-nbits: + description: + Set into the no BAR match register to configure the number of least + significant bits kept during inbound (PCIe -> AXI) address translations + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 64 + default: 32 + + msi-parent: true diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie.yaml new file mode 100644 index 000000000000..6887ccc339cc --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns-pcie.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/cdns-pcie.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence PCIe Core + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +properties: + cdns,max-outbound-regions: + description: maximum number of outbound regions + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + default: 32 + + phys: + description: + One per lane if more than one in the list. If only one PHY listed it must + manage all lanes. + minItems: 1 + maxItems: 16 + + phy-names: + items: + - const: pcie-phy + # FIXME: names when more than 1 diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml new file mode 100644 index 000000000000..b3df100705b0 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/pci-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCI Endpoint Controller Schema + +description: | + Common properties for PCI Endpoint Controller Nodes. + +maintainers: + - Kishon Vijay Abraham I <kishon@ti.com> + +properties: + $nodename: + pattern: "^pcie-ep@" + + max-functions: + description: Maximum number of functions that can be configured + allOf: + - $ref: /schemas/types.yaml#/definitions/uint8 + minimum: 1 + default: 1 + maximum: 255 + + max-link-speed: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 2, 3, 4 ] + + num-lanes: + description: maximum number of lanes + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + default: 1 + maximum: 16 + +required: + - compatible |