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author | Linus Walleij <linus.walleij@linaro.org> | 2019-10-21 01:00:41 +0200 |
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committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2019-10-29 14:24:51 +0100 |
commit | 8b3cc926223be73bb2ab5f9465f157fc27e06eca (patch) | |
tree | 2f3723cc2c90a096655f62a35b600c808f75fbae /Documentation/devicetree/bindings/mtd | |
parent | 5c1719a2b978f9a292d4fb3efa6d6525f36b7489 (diff) | |
download | linux-8b3cc926223be73bb2ab5f9465f157fc27e06eca.tar.bz2 |
mtd: add DT bindings for the Intel IXP4xx Flash
This adds device tree bindings for the Intel IXP4xx
flash controller, a simple physmap which however need a
specific big-endian or mixed-endian access pattern to the
memory.
Cc: devicetree@vger.kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'Documentation/devicetree/bindings/mtd')
-rw-r--r-- | Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt b/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt new file mode 100644 index 000000000000..4bdcb92ae381 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt @@ -0,0 +1,22 @@ +Flash device on Intel IXP4xx SoC + +This flash is regular CFI compatible (Intel or AMD extended) flash chips with +specific big-endian or mixed-endian memory access pattern. + +Required properties: +- compatible : must be "intel,ixp4xx-flash", "cfi-flash"; +- reg : memory address for the flash chip +- bank-width : width in bytes of flash interface, should be <2> + +For the rest of the properties, see mtd-physmap.txt. + +The device tree may optionally contain sub-nodes describing partitions of the +address space. See partition.txt for more detail. + +Example: + +flash@50000000 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + reg = <0x50000000 0x01000000>; + bank-width = <2>; +}; |