diff options
author | Piotr Sroka <piotrs@cadence.com> | 2019-09-26 09:13:21 +0100 |
---|---|---|
committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2019-10-04 18:02:24 +0200 |
commit | 5121b4219972c16e9ac92545a6743af2e99d4abc (patch) | |
tree | e90e1a88e2a54d6cb2a75292c6590544b1bc5a95 /Documentation/devicetree/bindings/mtd | |
parent | ec4ba01e894d3165e4d1ccbef782ef5593b708b4 (diff) | |
download | linux-5121b4219972c16e9ac92545a6743af2e99d4abc.tar.bz2 |
dt-bindings: mtd: Add Cadence NAND controller driver
Document the bindings used by Cadence NAND controller driver
Signed-off-by: Piotr Sroka <piotrs@cadence.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'Documentation/devicetree/bindings/mtd')
-rw-r--r-- | Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt new file mode 100644 index 000000000000..f3893c4d3c6a --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt @@ -0,0 +1,53 @@ +* Cadence NAND controller + +Required properties: + - compatible : "cdns,hp-nfc" + - reg : Contains two entries, each of which is a tuple consisting of a + physical address and length. The first entry is the address and + length of the controller register set. The second entry is the + address and length of the Slave DMA data port. + - reg-names: should contain "reg" and "sdma" + - #address-cells: should be 1. The cell encodes the chip select connection. + - #size-cells : should be 0. + - interrupts : The interrupt number. + - clocks: phandle of the controller core clock (nf_clk). + +Optional properties: + - dmas: shall reference DMA channel associated to the NAND controller + - cdns,board-delay-ps : Estimated Board delay. The value includes the total + round trip delay for the signals and is used for deciding on values + associated with data read capture. The example formula for SDR mode is + the following: + board delay = RE#PAD delay + PCB trace to device + PCB trace from device + + DQ PAD delay + +Child nodes represent the available NAND chips. + +Required properties of NAND chips: + - reg: shall contain the native Chip Select ids from 0 to max supported by + the cadence nand flash controller + +See Documentation/devicetree/bindings/mtd/nand.txt for more details on +generic bindings. + +Example: + +nand_controller: nand-controller@60000000 { + compatible = "cdns,hp-nfc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x60000000 0x10000>, <0x80000000 0x10000>; + reg-names = "reg", "sdma"; + clocks = <&nf_clk>; + cdns,board-delay-ps = <4830>; + interrupts = <2 0>; + nand@0 { + reg = <0>; + label = "nand-1"; + }; + nand@1 { + reg = <1>; + label = "nand-2"; + }; + +}; |