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author | Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> | 2019-10-22 22:30:18 +0530 |
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committer | Vinod Koul <vkoul@kernel.org> | 2019-11-06 22:37:22 +0530 |
commit | 535b4b0c050b79db6a63097599fc87a156db6b2c (patch) | |
tree | 6407eb2a30635c3292dbc65e4b385d20a66b7964 /Documentation/devicetree/bindings/dma/xilinx | |
parent | 96336cc043ba8f4999bbeb7a9a29b46fc05d2bc4 (diff) | |
download | linux-535b4b0c050b79db6a63097599fc87a156db6b2c.tar.bz2 |
dt-bindings: dmaengine: xilinx_dma: Fix formatting and style
Trivial formatting(keep compatible string one per line, caps change etc).
It doesn't modify the content of the binding.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1571763622-29281-3-git-send-email-radhey.shyam.pandey@xilinx.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/dma/xilinx')
-rw-r--r-- | Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index 99d06f9daee6..d4ba1cbcbc27 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -12,8 +12,10 @@ Xilinx AXI CDMA engine, it does transfers between memory-mapped source address and a memory-mapped destination address. Required properties: -- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or - "xlnx,axi-cdma-1.00.a"" +- compatible: Should be one of- + "xlnx,axi-vdma-1.00.a" + "xlnx,axi-dma-1.00.a" + "xlnx,axi-cdma-1.00.a" - #dma-cells: Should be <1>, see "dmas" property below - reg: Should contain VDMA registers location and length. - xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). @@ -29,7 +31,7 @@ Required properties: "m_axis_mm2s_aclk", "s_axis_s2mm_aclk" For CDMA: Required elements: "s_axi_lite_aclk", "m_axi_aclk" - FOR AXIDMA: + For AXIDMA: Required elements: "s_axi_lite_aclk" Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk" |