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| author | Frank Rowand <frank.rowand@sony.com> | 2017-06-22 09:15:39 -0700 |
|---|---|---|
| committer | Rob Herring <robh@kernel.org> | 2017-06-22 11:22:06 -0500 |
| commit | 076fb0c4b6e1f6883477d1e4ee89464924e64737 (patch) | |
| tree | 0ce0d0baecb6ed6e68129360a7283ca3f211228a /Documentation/devicetree/bindings/arm/cci.txt | |
| parent | 7782b1444645768f5f213eaff6994604c6c0e635 (diff) | |
| download | linux-076fb0c4b6e1f6883477d1e4ee89464924e64737.tar.bz2 | |
of: update ePAPR references to point to Devicetree Specification
The Devicetree Specification has superseded the ePAPR as the
base specification for bindings. Update files in Documentation
to reference the new document.
First reference to ePAPR in Documentation/devicetree/bindings/arm/cci.txt
is generic, remove it.
Some files are not updated because there is no hypervisor chapter
in the Devicetree Specification:
Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
Documenation/virtual/kvm/api.txt
Documenation/virtual/kvm/ppc-pv.txt
Signed-off-by: Frank Rowand <frank.rowand@sony.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/cci.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/cci.txt | 15 |
1 files changed, 4 insertions, 11 deletions
diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt index 0f2153e8fa7e..9600761f2d5b 100644 --- a/Documentation/devicetree/bindings/arm/cci.txt +++ b/Documentation/devicetree/bindings/arm/cci.txt @@ -11,13 +11,6 @@ clusters, through memory mapped interface, with a global control register space and multiple sets of interface control registers, one per slave interface. -Bindings for the CCI node follow the ePAPR standard, available from: - -www.power.org/documentation/epapr-version-1-1/ - -with the addition of the bindings described in this document which are -specific to ARM. - * CCI interconnect node Description: Describes a CCI cache coherent Interconnect component @@ -50,10 +43,10 @@ specific to ARM. as a tuple of cells, containing child address, parent address and the size of the region in the child address space. - Definition: A standard property. Follow rules in the ePAPR for - hierarchical bus addressing. CCI interfaces - addresses refer to the parent node addressing - scheme to declare their register bases. + Definition: A standard property. Follow rules in the Devicetree + Specification for hierarchical bus addressing. CCI + interfaces addresses refer to the parent node + addressing scheme to declare their register bases. CCI interconnect node can define the following child nodes: |