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authorLinu Cherian <linu.cherian@cavium.com>2017-06-22 17:35:37 +0530
committerWill Deacon <will.deacon@arm.com>2017-06-23 17:58:03 +0100
commite5b829de053d9994dfc8652ce558e90e3406c578 (patch)
tree6215ecb21bf1ebad7ff0e5a123369d1cb69d764d /Documentation/arm64
parent403e8c7c5bcaff3291a2c7012fe80f707a854d10 (diff)
downloadlinux-e5b829de053d9994dfc8652ce558e90e3406c578.tar.bz2
iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74
Cavium ThunderX2 SMMU implementation doesn't support page 1 register space and PAGE0_REGS_ONLY option is enabled as an errata workaround. This option when turned on, replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets. SMMU resource size checks are now based on SMMU option PAGE0_REGS_ONLY, since resource size can be either 64k/128k. For this, arm_smmu_device_dt_probe/acpi_probe has been moved before platform_get_resource call, so that SMMU options are set beforehand. Signed-off-by: Linu Cherian <linu.cherian@cavium.com> Signed-off-by: Geetha Sowjanya <geethasowjanya.akula@cavium.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/arm64')
-rw-r--r--Documentation/arm64/silicon-errata.txt1
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 10f2dddbf449..4693a328947a 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -62,6 +62,7 @@ stable kernels.
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
| Cavium | ThunderX SMMUv2 | #27704 | N/A |
+| Cavium | ThunderX2 SMMUv3| #74 | N/A |
| | | | |
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
| | | | |