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authorMark Brown <broonie@kernel.org>2022-05-03 18:02:31 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2022-05-04 15:30:28 +0100
commite33bb6461cd6ca0e0dad8392f0e3ee0179871e7a (patch)
tree8d281a8da6f711278a50d67c81ba5a29f46c71ba
parentc07d8017bceb82cbe5fedd129d072c59a53f5513 (diff)
downloadlinux-e33bb6461cd6ca0e0dad8392f0e3ee0179871e7a.tar.bz2
arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1
Remove the manual definitions for ID_AA64ISAR0_EL1 in favour of automatic generation. There should be no functional change. The only notable change is that 27:24 TME is defined rather than RES0 reflecting DDI0487H.a. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220503170233.507788-11-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
-rw-r--r--arch/arm64/include/asm/sysreg.h20
-rw-r--r--arch/arm64/tools/sysreg67
2 files changed, 67 insertions, 20 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index db07a01776d8..f5e02f27a5c9 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -196,7 +196,6 @@
#define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
#define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
-#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2)
@@ -747,25 +746,6 @@
/* Position the attr at the correct index */
#define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
-/* id_aa64isar0 */
-#define ID_AA64ISAR0_EL1_RNDR_SHIFT 60
-#define ID_AA64ISAR0_EL1_TLB_SHIFT 56
-#define ID_AA64ISAR0_EL1_TS_SHIFT 52
-#define ID_AA64ISAR0_EL1_FHM_SHIFT 48
-#define ID_AA64ISAR0_EL1_DP_SHIFT 44
-#define ID_AA64ISAR0_EL1_SM4_SHIFT 40
-#define ID_AA64ISAR0_EL1_SM3_SHIFT 36
-#define ID_AA64ISAR0_EL1_SHA3_SHIFT 32
-#define ID_AA64ISAR0_EL1_RDM_SHIFT 28
-#define ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
-#define ID_AA64ISAR0_EL1_CRC32_SHIFT 16
-#define ID_AA64ISAR0_EL1_SHA2_SHIFT 12
-#define ID_AA64ISAR0_EL1_SHA1_SHIFT 8
-#define ID_AA64ISAR0_EL1_AES_SHIFT 4
-
-#define ID_AA64ISAR0_EL1_TLB_RANGE_NI 0x0
-#define ID_AA64ISAR0_EL1_TLB_RANGE 0x2
-
/* id_aa64isar1 */
#define ID_AA64ISAR1_I8MM_SHIFT 52
#define ID_AA64ISAR1_DGH_SHIFT 48
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 8e39c718c1b8..4d8991574437 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -46,3 +46,70 @@
# feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
# item ACCDATA) though it may be more taseful to do something else.
+Sysreg ID_AA64ISAR0_EL1 3 0 0 6 0
+Enum 63:60 RNDR
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 59:56 TLB
+ 0b0000 NI
+ 0b0001 OS
+ 0b0010 RANGE
+EndEnum
+Enum 55:52 TS
+ 0b0000 NI
+ 0b0001 FLAGM
+ 0b0010 FLAGM2
+EndEnum
+Enum 51:48 FHM
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 47:44 DP
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 43:40 SM4
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 39:36 SM3
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 35:32 SHA3
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 31:28 RDM
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 27:24 TME
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 23:20 ATOMIC
+ 0b0000 NI
+ 0b0010 IMP
+EndEnum
+Enum 19:16 CRC32
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 15:12 SHA2
+ 0b0000 NI
+ 0b0001 SHA256
+ 0b0010 SHA512
+EndEnum
+Enum 11:8 SHA1
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 7:4 AES
+ 0b0000 NI
+ 0b0001 AES
+ 0b0010 PMULL
+EndEnum
+Res0 3:0
+EndSysreg