diff options
| author | Aurabindo Pillai <aurabindo.pillai@amd.com> | 2022-06-28 17:26:35 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-07-05 16:09:24 -0400 |
| commit | cfb979f71736361ec564d47d0a41f07e09983e32 (patch) | |
| tree | cb9e893a40ca9f52c982492523638f768dcabacc | |
| parent | c5da61cf5bab30059f22ea368702c445ee87171a (diff) | |
| download | linux-cfb979f71736361ec564d47d0a41f07e09983e32.tar.bz2 | |
drm/amd: Add debug mask for subviewport mclk switch
[Why&How]
Expose a new dc debug mask enum to force a subviewport memory clock switch
to facilitate easy testing.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/amd_shared.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1bd65b41ba4d..863e757d1f3e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1560,6 +1560,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) adev->dm.dc->debug.disable_clock_gate = true; + if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) + adev->dm.dc->debug.force_subvp_mclk_switch = true; + r = dm_dmub_hw_init(adev); if (r) { DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 2e02a6fc1717..1db21d13726d 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -248,6 +248,7 @@ enum DC_DEBUG_MASK { DC_DISABLE_DSC = 0x4, DC_DISABLE_CLOCK_GATING = 0x8, DC_DISABLE_PSR = 0x10, + DC_FORCE_SUBVP_MCLK_SWITCH = 0x20, }; enum amd_dpm_forced_level; |