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| author | Kamal Dasu <kdasu.kdev@gmail.com> | 2019-05-21 10:44:22 -0400 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2019-06-27 20:06:38 +0200 |
| commit | 78933218f5c658195124456904cc56e5b52988bd (patch) | |
| tree | 24de33665ab931e7d2571776cc6abc6c2495d73e | |
| parent | edd3e620ab15e66b0d5477dc3bd4732a2b3baddb (diff) | |
| download | linux-78933218f5c658195124456904cc56e5b52988bd.tar.bz2 | |
mtd: rawnand: brcmnand: fallback to detected ecc-strength, ecc-step-size
This change supports nand-ecc-step-size and nand-ecc-strength fields in
brcmnand DT node to be optional.
see: Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
If both nand-ecc-strength and nand-ecc-step-size are not specified in
device tree node for NAND, raw NAND layer does detect ECC information by
reading ONFI extended parameter page for parts using ONFI >= 2.1.
In case of non-ONFI NAND parts there could be a nand_id table entry with
ECC information. If there is valid device tree entry for nand-ecc-strength
and nand-ecc-step-size fields it still shall override the detected values.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| -rw-r--r-- | drivers/mtd/nand/raw/brcmnand/brcmnand.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index f368d1cb89f4..93ac1b5b8862 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -2136,6 +2136,17 @@ static int brcmnand_setup_dev(struct brcmnand_host *host) return -EINVAL; } + if (chip->ecc.mode != NAND_ECC_NONE && + (!chip->ecc.size || !chip->ecc.strength)) { + if (chip->base.eccreq.step_size && chip->base.eccreq.strength) { + /* use detected ECC parameters */ + chip->ecc.size = chip->base.eccreq.step_size; + chip->ecc.strength = chip->base.eccreq.strength; + dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n", + chip->ecc.size, chip->ecc.strength); + } + } + switch (chip->ecc.size) { case 512: if (chip->ecc.algo == NAND_ECC_HAMMING) |