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author | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-05 16:04:13 -0500 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-11 23:45:24 -0500 |
commit | 8dd99bca7bfa4b62753b556c45d26f45ec9da6e6 (patch) | |
tree | 105e54dc1f1cbc997c6deff99e1ac302ca1b1344 | |
parent | bdf530984d10b6b88b10a6d03057409a3f1c6897 (diff) | |
download | linux-8dd99bca7bfa4b62753b556c45d26f45ec9da6e6.tar.bz2 |
PCI: tegra: Fix argument order in tegra_pcie_phy_disable()
The tegra_pcie_phy_disable() path called pads_writel() with arguments in
the wrong order. Swap them to be the "value, offset" order expected by
pads_writel().
Fixes: 6fe7c187e026 ("PCI: tegra: Support per-lane PHYs")
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Thierry Reding <treding@nvidia.com>
CC: stable@vger.kernel.org # v4.7+
-rw-r--r-- | drivers/pci/host/pci-tegra.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index e2a8e4cab22e..6df5ed0ffe3c 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -859,7 +859,7 @@ static int tegra_pcie_phy_disable(struct tegra_pcie *pcie) /* override IDDQ */ value = pads_readl(pcie, PADS_CTL); value |= PADS_CTL_IDDQ_1L; - pads_writel(pcie, PADS_CTL, value); + pads_writel(pcie, value, PADS_CTL); /* reset PLL */ value = pads_readl(pcie, soc->pads_pll_ctl); |