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| author | Lee Jones <lee.jones@linaro.org> | 2012-03-08 09:02:02 +0000 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-03-16 19:48:46 +0000 |
| commit | f1949ea0d1f6034d38ce20089980b6b26d527c25 (patch) | |
| tree | 7c8e50314558d154008d720a4c03bc4ae5cc569c | |
| parent | 4905af0e13a665da5f72d2629e93161ba781d03b (diff) | |
| download | linux-f1949ea0d1f6034d38ce20089980b6b26d527c25.tar.bz2 | |
ARM: ux500: Enable PL310 Level 2 Cache Controller in Device Tree
This provides PL310 Level 2 Cache Controller Device Tree
support for all u8500 based devices.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | arch/arm/boot/dts/db8500.dtsi | 8 | ||||
| -rw-r--r-- | arch/arm/mach-ux500/cache-l2x0.c | 7 |
2 files changed, 14 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index 614a471df4a7..ce3b56fb9132 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -29,6 +29,14 @@ <0xa0410100 0x100>; }; + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xa0412000 0x1000>; + interrupts = <0 13 4>; + cache-unified; + cache-level = <2>; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 7 0x4>; diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index da5569d83d58..77a75ed0df67 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -5,6 +5,8 @@ */ #include <linux/io.h> +#include <linux/of.h> + #include <asm/cacheflush.h> #include <asm/hardware/cache-l2x0.h> #include <mach/hardware.h> @@ -45,7 +47,10 @@ static int __init ux500_l2x0_init(void) ux500_l2x0_unlock(); /* 64KB way size, 8 way associativity, force WA */ - l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); + if (of_have_populated_dt()) + l2x0_of_init(0x3e060000, 0xc0000fff); + else + l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); /* * We can't disable l2 as we are in non secure mode, currently |