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| author | Stéphane Marchesin <marcheu@chromium.org> | 2014-05-22 20:32:48 -0700 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-06-09 12:02:47 +0200 |
| commit | ca185c68ed626bf91e22e41e2358d39e8508453c (patch) | |
| tree | 6c6c5ed290ae6dc8b38d5906cdfd28aa264edd1a | |
| parent | 143b1df23e81df52e2a96e1848acabfb38a0c4e6 (diff) | |
| download | linux-ca185c68ed626bf91e22e41e2358d39e8508453c.tar.bz2 | |
drm/tegra: sor - Change power down ordering
Lanes are powered up in decreasing order. Power them down in increasing
order for consistency.
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | drivers/gpu/drm/tegra/sor.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 735c76babdf2..f082ea22f32e 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -748,7 +748,7 @@ static int tegra_sor_power_down(struct tegra_sor *sor) tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); /* stop lane sequencer */ - value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | + value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); |