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authorFabio Estevam <fabio.estevam@freescale.com>2015-06-26 14:10:54 -0300
committerShawn Guo <shawnguo@kernel.org>2015-07-13 16:35:30 +0800
commit05e062f92c917b14ffa944e4a98e5348b53b1390 (patch)
tree29fabd2da2c71f45f24b9d2ae5572e6097080bca
parentd770e558e21961ad6cfdf0ff7df0eb5d7d4f0754 (diff)
downloadlinux-05e062f92c917b14ffa944e4a98e5348b53b1390.tar.bz2
clk: imx: clk-imx6q: Provide initial IPU clock settings for mx6dl
Currently it is not possible to use HDMI and LVDS at the same time on a imx6dl-sabresd board. Fix this usecase by setting IMX6QDL_CLK_PLL3_PFD1_540M to 540MHz and also by setting it as the parent of IMX6QDL_CLK_IPU1_SEL. Based on the configuration done in the FSL kernel. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--drivers/clk/imx/clk-imx6q.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index d046f8e43de8..c507bcad2c37 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -494,6 +494,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
}
+ clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000);
+ if (clk_on_imx6dl())
+ clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
+
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);