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authorAlexandre Belloni <alexandre.belloni@bootlin.com>2019-02-19 15:28:08 +0100
committerAlexandre Belloni <alexandre.belloni@bootlin.com>2019-05-21 17:42:09 +0200
commitbd5d3873de70529b3a810c8d3fda82b6423c1ba4 (patch)
tree3f245c93930add0d04e110c3465f1c85f627e23f
parentd77a1de7f61e0380cd00007d7131471be0def10f (diff)
downloadlinux-bd5d3873de70529b3a810c8d3fda82b6423c1ba4.tar.bz2
ARM: dts: at91: sama5d3: switch to new sckc bindings
Remove the child nodes of the sckc as they are not necessary anymore. Also, switch to the new atmel,sama5d3-sckc compatible string to use the proper startup time for the RC oscillator (500 µs instead of 75). Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
-rw-r--r--arch/arm/boot/dts/at91-wb50n.dtsi2
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi27
2 files changed, 5 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/at91-wb50n.dtsi b/arch/arm/boot/dts/at91-wb50n.dtsi
index 85692c8ef2b1..4ed8500a5cb8 100644
--- a/arch/arm/boot/dts/at91-wb50n.dtsi
+++ b/arch/arm/boot/dts/at91-wb50n.dtsi
@@ -42,7 +42,7 @@
clock-frequency = <12000000>;
};
-&slow_osc {
+&clk32k {
atmel,osc-bypass;
};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 02198772eb81..72b198f928c6 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1372,30 +1372,11 @@
status = "disabled";
};
- sckc@fffffe50 {
- compatible = "atmel,at91sam9x5-sckc";
+ clk32k: sckc@fffffe50 {
+ compatible = "atmel,sama5d3-sckc";
reg = <0xfffffe50 0x4>;
-
- slow_rc_osc: slow_rc_osc {
- compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-accuracy = <50000000>;
- atmel,startup-time-usec = <75>;
- };
-
- slow_osc: slow_osc {
- compatible = "atmel,at91sam9x5-clk-slow-osc";
- #clock-cells = <0>;
- clocks = <&slow_xtal>;
- atmel,startup-time-usec = <1200000>;
- };
-
- clk32k: slowck {
- compatible = "atmel,at91sam9x5-clk-slow";
- #clock-cells = <0>;
- clocks = <&slow_rc_osc &slow_osc>;
- };
+ clocks = <&slow_xtal>;
+ #clock-cells = <0>;
};
rtc@fffffeb0 {