summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLeo Li <sunpeng.li@amd.com>2019-07-25 13:12:24 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-08-02 10:17:57 -0500
commitd9ec5cfd5a2eca87b7c5f697ae07b5c9ae9b771f (patch)
tree64d014186479a744d13d79d53db5435b68b40ada
parentd196bbbc28fab82624f7686f8b0da8e8644b6e6a (diff)
downloadlinux-d9ec5cfd5a2eca87b7c5f697ae07b5c9ae9b771f.tar.bz2
drm/amd/display: Use switch table for dc_to_smu_clock_type
Using a static int array will cause errors if the given dm_pp_clk_type is out-of-bounds. For robustness, use a switch table, with a default case to handle all invalid values. v2: 0 is a valid clock type for smu_clk_type. Return SMU_CLK_COUNT instead on invalid mapping. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c37
1 files changed, 25 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index ea0e17e87c08..f4cfa0caeba8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -151,18 +151,31 @@ static void get_default_clock_levels(
static enum smu_clk_type dc_to_smu_clock_type(
enum dm_pp_clock_type dm_pp_clk_type)
{
-#define DCCLK_MAP_SMUCLK(dcclk, smuclk) \
- [dcclk] = smuclk
-
- static int dc_clk_type_map[] = {
- DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_DISPLAY_CLK, SMU_DISPCLK),
- DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_ENGINE_CLK, SMU_GFXCLK),
- DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_MEMORY_CLK, SMU_MCLK),
- DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_DCEFCLK, SMU_DCEFCLK),
- DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_SOCCLK, SMU_SOCCLK),
- };
-
- return dc_clk_type_map[dm_pp_clk_type];
+ enum smu_clk_type smu_clk_type = SMU_CLK_COUNT;
+
+ switch (dm_pp_clk_type) {
+ case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
+ smu_clk_type = SMU_DISPCLK;
+ break;
+ case DM_PP_CLOCK_TYPE_ENGINE_CLK:
+ smu_clk_type = SMU_GFXCLK;
+ break;
+ case DM_PP_CLOCK_TYPE_MEMORY_CLK:
+ smu_clk_type = SMU_MCLK;
+ break;
+ case DM_PP_CLOCK_TYPE_DCEFCLK:
+ smu_clk_type = SMU_DCEFCLK;
+ break;
+ case DM_PP_CLOCK_TYPE_SOCCLK:
+ smu_clk_type = SMU_SOCCLK;
+ break;
+ default:
+ DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
+ dm_pp_clk_type);
+ break;
+ }
+
+ return smu_clk_type;
}
static enum amd_pp_clock_type dc_to_pp_clock_type(