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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2011-05-12 22:17:20 +0100 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2011-06-04 10:41:12 -0700 |
| commit | c8ebc2b076ad9e1833cb4f7f1a6f30b4786a2a09 (patch) | |
| tree | 68eb78019ecddcb91c025f1f0d2dd1c0e3a2ba64 | |
| parent | d3bcb75776a10ee4b67afe6156fd927b9da77d03 (diff) | |
| download | linux-c8ebc2b076ad9e1833cb4f7f1a6f30b4786a2a09.tar.bz2 | |
drm/915: fix relaxed tiling on gen2: tile height
A tile on gen2 has a size of 2kb, stride of 128 bytes and 16 rows.
Userspace was broken and assumed 8 rows. Chris Wilson noted that the
kernel unfortunately can't reliable check that because libdrm rounds
up the size to the next bucket.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 7b8feff53c0d..12d32579b951 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1449,8 +1449,9 @@ i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) * edge of an even tile row (where tile rows are counted as if the bo is * placed in a fenced gtt region). */ - if (IS_GEN2(dev) || - (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) + if (IS_GEN2(dev)) + tile_height = 16; + else if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) tile_height = 32; else tile_height = 8; |