diff options
| author | Stephen Boyd <sboyd@codeaurora.org> | 2015-01-29 15:38:13 -0800 |
|---|---|---|
| committer | Michael Turquette <mturquette@linaro.org> | 2015-02-25 12:08:39 -0800 |
| commit | 4be8fc04700aafeb3c8a9c10ece5652e08ec0e94 (patch) | |
| tree | ba872a77f78d9c7146a345d15beba8896050ca0c | |
| parent | 84b919fdb8559a8cd5432d8fa0002219df59cb32 (diff) | |
| download | linux-4be8fc04700aafeb3c8a9c10ece5652e08ec0e94.tar.bz2 | |
clk: qcom: Add PLL4 vote clock
This clock is needed for most audio clock frequencies. Add it.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
| -rw-r--r-- | drivers/clk/qcom/gcc-msm8960.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c index b0b562b9ce0e..e60feffc10a1 100644 --- a/drivers/clk/qcom/gcc-msm8960.c +++ b/drivers/clk/qcom/gcc-msm8960.c @@ -48,6 +48,17 @@ static struct clk_pll pll3 = { }, }; +static struct clk_regmap pll4_vote = { + .enable_reg = 0x34c0, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "pll4_vote", + .parent_names = (const char *[]){ "pll4" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + static struct clk_pll pll8 = { .l_reg = 0x3144, .m_reg = 0x3148, @@ -3023,6 +3034,7 @@ static struct clk_branch rpm_msg_ram_h_clk = { static struct clk_regmap *gcc_msm8960_clks[] = { [PLL3] = &pll3.clkr, + [PLL4_VOTE] = &pll4_vote, [PLL8] = &pll8.clkr, [PLL8_VOTE] = &pll8_vote, [PLL14] = &pll14.clkr, @@ -3247,6 +3259,7 @@ static const struct qcom_reset_map gcc_msm8960_resets[] = { static struct clk_regmap *gcc_apq8064_clks[] = { [PLL3] = &pll3.clkr, + [PLL4_VOTE] = &pll4_vote, [PLL8] = &pll8.clkr, [PLL8_VOTE] = &pll8_vote, [PLL14] = &pll14.clkr, |