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| author | Vandita Kulkarni <vandita.kulkarni@intel.com> | 2019-03-25 16:56:41 +0530 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2019-04-10 15:37:26 +0300 |
| commit | c5b81a325263a891d5811aabe938c87e03db4c37 (patch) | |
| tree | c33235355fec3e3d2260706a33362eb1a30594c4 | |
| parent | 174221e8491588aa9d44ebfa3242bea11eacc64f (diff) | |
| download | linux-c5b81a325263a891d5811aabe938c87e03db4c37.tar.bz2 | |
drm/i915/icl: Ungate ddi clocks before IO enable
IO enable sequencing needs ddi clocks enabled.
These clocks will be gated at a later point in
the enable sequence.
v2: Fix the commit header (Uma)
v3: Remove the redundant read (Ville)
Fixes: 949fc52af19e ("drm/i915/icl: add pll mapping for DSI")
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1553513202-13863-1-git-send-email-vandita.kulkarni@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/icl_dsi.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index 6fc48479c97b..be1cfbced8e9 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -602,6 +602,12 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); } I915_WRITE(DPCLKA_CFGCR0_ICL, val); + + for_each_dsi_port(port, intel_dsi->ports) { + val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); + } + I915_WRITE(DPCLKA_CFGCR0_ICL, val); + POSTING_READ(DPCLKA_CFGCR0_ICL); mutex_unlock(&dev_priv->dpll_lock); |